System verilog 如何使用Xiling VIP IP通过AXI流发送数据
我正在尝试使用AXI流验证IP,但我不知道如何在从属模式下使用它。如何从代理获取数据:System verilog 如何使用Xiling VIP IP通过AXI流发送数据,system-verilog,xilinx,vivado,test-bench,System Verilog,Xilinx,Vivado,Test Bench,我正在尝试使用AXI流验证IP,但我不知道如何在从属模式下使用它。如何从代理获取数据: import axi4stream_vip_v1_0_1_pkg::*; import axis_vip_master_pkg::*; import axis_vip_slave_pkg::*; module shift_register_vip(); logic aclk; logic aresetn; logic [63:0] in_tdata; logic
import axi4stream_vip_v1_0_1_pkg::*;
import axis_vip_master_pkg::*;
import axis_vip_slave_pkg::*;
module shift_register_vip();
logic aclk;
logic aresetn;
logic [63:0] in_tdata;
logic in_tvalid;
logic in_tready;
logic [23:0] out_tdata;
logic out_tvalid;
logic out_tready;
axis_vip_master vip_master(.aclk(aclk), .aresetn(aresetn), .m_axis_tdata(in_tdata), .m_axis_tvalid(in_tvalid), .m_axis_tready(in_tready));
shift_register dut(.aclk(aclk), .aresetn(aresetn), .s_axis_data(in_tdata), .s_axis_valid(in_tvalid), .s_axis_ready(in_tready), .m_axis_data(out_tdata), .m_axis_valid(out_tvalid), .m_axis_ready(out_tready));
axis_vip_slave vip_slave(.aclk(aclk), .aresetn(aresetn), .s_axis_tdata(out_tdata), .s_axis_tvalid(out_tvalid), .s_axis_tready(out_tready));
initial aclk = 1;
always #5ns aclk <= ~aclk;
axis_vip_master_mst_t master_agent;
axis_vip_slave_slv_t slave_agent;
mailbox mbx;
mailbox sbx;
task generator();
for (int i = 0; i < 255; i++) begin
logic [7:0] word = $random();
mbx.put(word);
sbx.put(word);
end
endtask
task run_master();
while (1) begin
axi4stream_transaction trans = master_agent.driver.create_transaction();
logic [63:0] din;
for (int i = 0; i < 8; i++) begin
mbx.get(din[i * 8 +: 8]);
end
trans.set_data_beat(din);
master_agent.driver.send(trans);
end
endtask
initial begin
master_agent = new("master", vip_master.inst.IF);
slave_agent = new("slave", vip_slave.inst.IF);
mbx = new();
sbx = new();
master_agent.start_master();
slave_agent.start_slave();
aresetn <= 0;
repeat (4) @(posedge aclk);
aresetn <= 1;
fork
generator();
run_master();
join
end
endmodule
导入axi4stream_vip_v1_0_1_包装::*;
导入axis_vip_master_包装::*;
导入axis_vip_slave_包装::*;
模块移位寄存器vip();
逻辑aclk;
逻辑实验;
数据中的逻辑[63:0];
图瓦利德的逻辑;
逻辑推理;
逻辑[23:0]输出数据;
逻辑输出;
逻辑推理;
axis_vip_master vip_master(.aclk(aclk),.aresetn(aresetn),.m_axis_tdata(in_tdata),.m_axis_tvalid(in_tvalid),.m_axis_tRady(in_tRady));
移位寄存器dut(.aclk(aclk),.aresetn(aresetn),.s_轴数据(in_-tdata),.s_轴有效(in_-tvalid),.s_轴就绪(in_-tready),.m_轴数据(out-tdata),.m_轴有效(out_-tdalid),.m_轴就绪(out_-tready));
axis_vip_slave vip_slave(.aclk(aclk),.aresetn(aresetn),.s_axis_tdata(out_tdata),.s_axis_tvalid(out_tvalid),.s_axis_tready(out_tready));
初始aclk=1;
始终#5ns aclk您可以使用以下命令打印每个从属事务:
axi4stream_monitor_transaction mon_trans;
xil_axi4stream_data_byte InputData[2];
slave_agent.set_verbosity(0);
slave_agent.start_monitor();
forever begin
slave_agent.monitor.item_collected_port.get(mon_trans);
mon_trans.get_data(InputData);
$display("Transaction: %d, %d", InputData[0], InputData[1]);
end