Vhdl Quartus后期合成中的问题——输出为xxxxxxxx
我已经编写了一个vhdl代码，我想在FPGA中运行它，该代码在ghdl和Quartus 2预合成（RTL模拟）中运行良好，但当我在网关级模拟中运行时，它显示数据为xxxxxxx。我无法找出问题所在。有人能帮我吗 ---设备代码Vhdl Quartus后期合成中的问题——输出为xxxxxxxx,vhdl,fpga,quartus,Vhdl,Fpga,Quartus,我已经编写了一个vhdl代码，我想在FPGA中运行它，该代码在ghdl和Quartus 2预合成（RTL模拟）中运行良好，但当我在网关级模拟中运行时，它显示数据为xxxxxxx。我无法找出问题所在。有人能帮我吗 ---设备代码 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity SimpleCalculator is port ( data_in :in std_logic_vector(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SimpleCalculator is
port ( data_in :in std_logic_vector(3 downto 0);
data_valid : in std_logic;
data_out : out std_logic_vector(7 downto 0);
clk, reset: in std_logic);
end entity SimpleCalculator;
architecture behave of SimpleCalculator is
----------------------------------
-- defining main state consisting of states of main thread
----------------------------------
type main_state is (main_idle,main_read0,main_read1,main_read2,main_read3,main_read4,main_calc);
signal next_mainstate: main_state;
-- below code creates two dimensional
-- array of 8 inputs with 16 bits each
type inputs_bit is array(0 to 4) of std_logic_vector(3 downto 0);
signal input_array : inputs_bit;
signal calc_start : std_logic;
signal calc_done : std_logic;
------------------------------
-- defining signals and states for calc thread
------------------------------
type calc_state is (calc_idle,calc_check_inputs,calc_running,calc_error);
signal calcstate : calc_state;
-----------------------------
begin
main: process(clk,reset,data_valid,next_mainstate,calc_done)
variable nstate:main_state;
--variable count: integer:=0;
begin
nstate := next_mainstate;
case next_mainstate is
when main_idle =>
if(data_valid = '1' ) then
nstate:= main_read0;
else
nstate:= main_idle;
end if;
when main_read0 =>
input_array(0) <= data_in;
nstate:=main_read1;
when main_read1 =>
input_array(1) <= data_in;
nstate:=main_read2;
when main_read2 =>
input_array(2) <= data_in;
nstate:=main_read3;
when main_read3 =>
input_array(3) <= data_in;
nstate:=main_read4;
when main_read4 =>
input_array(4) <= data_in;
nstate:=main_calc;
calc_start <= '1';
when main_calc =>
calc_start <= '0';
if(calc_done ='1') then
nstate:= main_idle;
else
nstate:=main_calc;
end if;
when others => null;
end case;
if(clk'event and clk = '1') then
if(reset = '1') then
next_mainstate <= main_idle;
else
next_mainstate <= nstate;
end if;
end if;
end process main;
------------------------------------------------
--calc fsm
---------------------------------------------
calc: process(clk,reset,calc_start,calcstate)
variable nstate:calc_state;
begin
nstate := calcstate;
case calcstate is
when calc_idle =>
if(calc_start = '1') then
nstate := calc_check_inputs;
else
nstate := calc_idle;
end if;
when calc_check_inputs =>
if(input_array(0) = "1010" and input_array(1) < "1010" and input_array(2) > "1011"
and input_array(3) < "1010" and input_array(4) = "1011") then
nstate := calc_running;
else
nstate := calc_error;
end if;
-- check for correct sequence
when calc_error =>
data_out <= "11111111";
when calc_running =>
case input_array(2) is
when "1100" =>
data_out <= std_logic_vector(unsigned(input_array(1)) * unsigned(input_array(3)) ) after 1 ns;
when "1101" =>
data_out <= "0000" & std_logic_vector(unsigned(input_array(1)) + unsigned(input_array(3)) ) after 1 ns;
when "1110" =>
data_out <= "0000" & std_logic_vector(unsigned(input_array(1)) - unsigned(input_array(3)) ) after 1 ns;
when "1111" =>
data_out <= "0000" & std_logic_vector(unsigned(input_array(1)) / unsigned(input_array(3)) ) after 1 ns;
when others => null;
end case;
calc_done <='1';
nstate := calc_idle;
when others => null;
end case;
if(clk'event and clk = '1') then
if(reset = '1') then
calcstate <= calc_idle;
else
calcstate <= nstate;
end if;
end if;
end process calc;
end behave;
--- **testbench**
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity Simplecalculator_tb is
end entity;
architecture behave of Simplecalculator_tb is
signal data_in : std_logic_vector(3 downto 0);
signal data_valid : std_logic:= '0';
signal data_out : std_logic_vector(7 downto 0);
signal clk, reset: std_logic:= '0';
file stimulus_file: text is in "calci_inputs.txt";
file result_file: text is in "calci_result.txt";
component SimpleCalculator is
port ( data_in :in std_logic_vector(3 downto 0);
data_valid : in std_logic;
data_out : out std_logic_vector(7 downto 0);
clk, reset: in std_logic);
end component;
begin
-- 10 ns clock.
clk <= not clk after 5 ns;
process
variable L: line;
variable next_number_input: bit_vector(3 downto 0);
variable next_number_output: bit_vector(7 downto 0);
begin
reset <= '1';
data_valid <= '0';
wait until clk ='1';
reset <= '0';
data_valid <= '1';
wait until clk ='1';
data_valid <= '0';
while( not endfile(stimulus_file)) loop
readline(stimulus_file,L);
read(L,next_number_input);
data_in <= To_StdLogicVector(next_number_input);
wait until clk='1';
assert false report "Sent item " severity note;
end loop;
assert false report "Sent all items " severity note;
wait for 20 ns;
assert false report "Received done " severity note;
readline(result_file,L);
read(L,next_number_output);
if(data_out = To_StdLogicVector(next_number_output)) then
assert false report "SUCCESS: got the correct result." severity note;
else
assert false report "FAILURE: incorrect result! " severity ERROR;
end if;
wait;
end process;
dut : SimpleCalculator port map
( data_in => data_in, data_valid => data_valid, data_out => data_out, clk => clk,
reset => reset);
end behave;
ieee库；
使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
实体SimpleCalculator是
端口（数据输入：标准逻辑向量（3到0）；
数据有效：在标准逻辑中；
数据输出：输出标准逻辑向量（7到0）；
时钟、复位：在标准逻辑中）；
终端实体简单计算器；
SimpleCalculator的体系结构表现为
----------------------------------
--定义由主线程状态组成的主状态
----------------------------------
类型main_state为（main_idle、main_read0、main_read1、main_read2、main_read3、main_read4、main_calc）；
信号下一个主状态：主状态；
--下面的代码创建二维
--8个输入的阵列，每个16位
类型输入_位是标准_逻辑_向量（3到0）的数组（0到4）；
信号输入_阵列：输入_位；
信号计算启动：标准逻辑；
信号计算完成：标准逻辑；
------------------------------
--定义calc线程的信号和状态
------------------------------
类型calc_状态为（calc_空闲、calc_检查输入、calc_运行、calc_错误）；
信号calcstate：calc_状态；
-----------------------------
开始
主：过程（时钟、复位、数据有效、下一主状态、计算完成）
变量nstate：主状态；
--变量计数：整数：=0；
开始
nstate:=下一个主状态；
下一个案件是
主_空闲时=>
如果（数据有效='1'），则
nstate:=main_read0；
其他的
nstate:=主空闲；
如果结束；
当main_read0=>
输入_数组（0）
输入_数组（1）
输入_数组（2）
输入_数组（3）
输入_阵列（4）门级模拟包括设计原语（例如触发器）的计时，因此必须遵守触发器数据的设置和保持时间，否则触发器可能会在输出上产生“X”
编写测试台代码时没有考虑到这一点；例如：
wait until clk ='1';
reset <= '0';
等待clk='1'；
有关运行后期synth模拟的一些提示，请参阅重置。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity Simplecalculator_tb is
end entity;
architecture behave of Simplecalculator_tb is
signal data_in : std_logic_vector(3 downto 0):= (others => '0');
signal data_valid : std_logic:= '0';
signal data_out : std_logic_vector(7 downto 0);
signal clk, reset: std_logic:= '0';
file stimulus_file: text is in "/home/student/pavanpalla/lab_5/calci_inputs.txt";
file result_file: text is in "/home/student/pavanpalla/lab_5/calci_result.txt";
component SimpleCalculator is
port ( data_in :in std_logic_vector(3 downto 0);
data_valid : in std_logic;
data_out : out std_logic_vector(7 downto 0);
clk, reset: in std_logic);
end component;
begin
-- 10 ns clock.
clk <= not clk after 20 ns;
process
variable L: line;
variable next_number_input: bit_vector(3 downto 0);
variable next_number_output: bit_vector(7 downto 0);
begin
reset <= '1';
data_valid <= '0';
wait until clk ='1';
reset <= '0' after 2 ns;
data_valid <= '1' after 2 ns;
wait until clk ='1';
data_valid <= '0' after 2 ns;
while( not endfile(stimulus_file)) loop
readline(stimulus_file,L);
read(L,next_number_input);
data_in <= To_StdLogicVector(next_number_input) after 10 ns;
wait until clk='1';
assert false report "Sent item " severity note;
end loop;
assert false report "Sent all items " severity note;
wait for 50 ns;
assert false report "Received done " severity note;
readline(result_file,L);
read(L,next_number_output);
if(data_out = To_StdLogicVector(next_number_output)) then
assert false report "SUCCESS: got the correct result." severity note;
else
assert false report "FAILURE: incorrect result! " severity ERROR;
end if;
wait;
end process;
dut : SimpleCalculator port map
( data_in => data_in, data_valid => data_valid, data_out => data_out, clk => clk,
reset => reset);
end behave;
wait until clk ='1';
reset <= '0';