为什么在ARM64指令集中找不到ARM32指令的机器代码

由于ARM32机器指令可以直接在ARM64处理器上执行，我认为ARM32指令的机器代码

add r0，r0，r1

应该与这两条ARM64指令中的一条相同：

add w0, w0, w1
add x0, x0, x1

然而，在objdump一些.o文件之后，我发现情况并非如此。它们的机器代码如下所示：

e0800001    add r0, r0, r1
0b010000    add w0, w0, w1
8b010000    add x0, x0, x1

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然后我试图找到e0800001在ARM64中的含义，但在ARM64中找不到任何以0xe0开头的操作码。我在

上搜索了有关ARM64操作码的文档。你在做很多毫无根据的假设

引述：

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因此，ARMv8 CPU在任何异常级别都可能不支持AArch32。这种CPU的一个例子是苹果的A11，它在iPhone 8和X中都有特点。

“因为ARM32机器指令可以直接在ARM64处理器上执行，”-它们不能，你必须在之前切换指令集，就像你需要在Thumb（T32）和ARM（A32）之间切换一样。请参阅。内核可以在异常返回时在AArch64和AArch32之间切换。如果您想了解arm指令，请参阅实际的arm文档。arm文档清楚地记录了AArch32与AArch64、如何切换模式等。您不了解arm文档的哪一部分？arm（A32）与Thumb（T32）的区别即使在同一应用程序中，也可以通过

BX

指令“直接”切换到thumb或从thumb切换到thumb。根据性能需要在A32/T32之间切换并不罕见。AArch32/AArch64之间的切换必须通过内核级别完成，例如，Linux不支持同时使用这两种指令集的应用程序，因此每个应用程序都是32位或64位的。因此，切换不是那么容易/直接。

A1.3.2 The Armv8 instruction sets

In Armv8 the possible instruction sets depend on the Execution state: AArch64 AArch64 state supports only a single instruction set, called A64. This is a fixed-length instruction set that uses 32-bit instruction encodings. For information on the A64 instruction set, see Chapter C3 A64 Instruction Set Overview. AArch32 AArch32 state supports the following instruction sets: A32 This is a fixed-length instruction set that uses 32-bit instruction encodings T32 This is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings. EL3, bits [15:12] EL3 Exception level handling. Defined values are: 0b0000 EL3 is not implemented. 0b0001 EL3 can be executed in AArch64 state only. 0b0010 EL3 can be executed in either AArch64 or AArch32 state. All other values are reserved. EL2, bits [11:8] EL2 Exception level handling. Defined values are: 0b0000 EL2 is not implemented. 0b0001 EL2 can be executed in AArch64 state only. 0b0010 EL2 can be executed in either AArch64 or AArch32 state. All other values are reserved. EL1, bits [7:4] EL1 Exception level handling. Defined values are: 0b0001 EL1 can be executed in AArch64 state only. 0b0010 EL1 can be executed in either AArch64 or AArch32 state. All other values are reserved. EL0, bits [3:0] EL0 Exception level handling. Defined values are: 0b0001 EL0 can be executed in AArch64 state only. 0b0010 EL0 can be executed in either AArch64 or AArch32 state. All other values are reserved.