Vhdl 有源HDL中的结构结构仿真

我已经编写了两个代码，成功地模拟了ISE设计套装：

-- 2X1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux2to1_pkg is
component mux2to1  
    port(d1,d0: in std_logic;
         s: in std_logic;
         f: out std_logic);
end component;
end mux2to1_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
port(d1,d0: in std_logic;
     s: in std_logic;
     f: out std_logic);
end mux2to1;          
architecture behavioral of mux2to1 is
begin
f <= (d0 and not s) or
     (d1 and     s);
end behavioral;

问题是，当我想在活动HDL中模拟MUX6to1时，输出根本不会改变。这个节目的秘密是什么？Ty.

使用此试验台：

library ieee;
use ieee.std_logic_1164.all;
entity mdl_tb is
end entity;

library ieee;
use ieee.numeric_std.all;
architecture sim of mdl_tb is
  signal s_d : std_logic_vector(8 downto 0) := (others => '0');
  signal f   : std_logic;
begin
  dut_e : entity work.mux6to1
    port map(d => s_d(5 downto 0),
             s => s_d(8 downto 6),
             f => f);
  process is
  begin
    wait for 1 ns;
    s_d <= std_logic_vector(unsigned(s_d) + 1);
  end process;
end architecture;

顺便说一句，如果跳过组件声明和相关包，您可以通过以下代码显著减少代码：

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
  port(d1,d0: in std_logic;
    s: in std_logic;
    f: out std_logic);
end mux2to1;
architecture behavioral of mux2to1 is
begin
  f <= d0 when (s = '0') else d1;
end behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux6to1 is
  port(d: in std_logic_vector(5 downto 0);
    s: in std_logic_vector(2 downto 0);
    f: out std_logic);
end mux6to1;
architecture structural of mux6to1 is
  signal m1,m2,m3,m4: std_logic;
begin
  mux1: entity work.mux2to1 port map(d(5),d(4),s(0),m1);
  mux2: entity work.mux2to1 port map(d(3),d(2),s(0),m2);
  mux3: entity work.mux2to1 port map(d(1),d(0),s(0),m3);
  mux4: entity work.mux2to1 port map(m2,m3,s(1),m4);
  mux5: entity work.mux2to1 port map(m1,m4,s(2),f);
end structural;

IEEE库；
使用IEEE.STD_LOGIC_1164.all；
实体mux2to1是
端口（d1，d0：标准逻辑中；
s：标准逻辑；
f：输出标准（U逻辑）；
结束mux2to1；
mux2to1的体系结构是
开始
F
# Workspace "prod" create under current and open this workspace
workspace create prod
# Design "prod" create under current workspace
design create -a prod .
# Create to directory under workspace
cd $DSN/..
# Compile
acom ../mdl.vhd
acom ../mdl_tb.vhd
# Load module for simulation
asim work.mdl_tb
# Waveform add
add wave /mdl_tb/*
# Run
run 600 ns 

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
  port(d1,d0: in std_logic;
    s: in std_logic;
    f: out std_logic);
end mux2to1;
architecture behavioral of mux2to1 is
begin
  f <= d0 when (s = '0') else d1;
end behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux6to1 is
  port(d: in std_logic_vector(5 downto 0);
    s: in std_logic_vector(2 downto 0);
    f: out std_logic);
end mux6to1;
architecture structural of mux6to1 is
  signal m1,m2,m3,m4: std_logic;
begin
  mux1: entity work.mux2to1 port map(d(5),d(4),s(0),m1);
  mux2: entity work.mux2to1 port map(d(3),d(2),s(0),m2);
  mux3: entity work.mux2to1 port map(d(1),d(0),s(0),m3);
  mux4: entity work.mux2to1 port map(m2,m3,s(1),m4);
  mux5: entity work.mux2to1 port map(m1,m4,s(2),f);
end structural;