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vhdl分配索引为的std_逻辑_向量的特定位失败

vhdl

vhdl分配索引为的std_逻辑_向量的特定位失败,vhdl,Vhdl,我试着这么做 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_8to1 is Port ( Y : in STD_LOGIC_VECTOR (0 to 7); S : in STD_LOGIC_VECTOR (2 downto 0); F : out S

我试着这么做

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_8to1 is
    Port ( Y : in  STD_LOGIC_VECTOR (0 to 7);
           S : in  STD_LOGIC_VECTOR (2 downto 0);
           F : out  STD_LOGIC);
end mux_8to1;

architecture Behavioral of mux_8to1 is
begin
  run: for i in 0 to 7 generate
    F <= Y(i) when S = i else
         '0';
  end generate run;

end Behavioral;

IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
使用IEEE.STD_LOGIC_ARITH.ALL；
使用IEEE.STD_LOGIC_UNSIGNED.ALL；
实体mux_8to1是
端口（Y：标准逻辑向量（0到7）；
S：标准逻辑向量（2到0）；
F：输出标准（U逻辑）；
结束mux_8to1；
mux_8to1的体系结构是
开始
运行：为0到7中的i生成

F合成工具将展开生成循环，结果是：


F <= Y(0) when S = 0 else '0';
F <= Y(1) when S = 1 else '0';
...
F <= Y(7) when S = 7 else '0';


为了演示如何使用循环生成，代码为：


process (Y, S) is
begin
  F <= 'X';  -- Default to avoid latch if no resulting driver in loop
  for i in 0 to 7 loop
    if S = i then
      F <= Y(i);
    end if;
  end loop;
end process;


简而言之：


F <= Y(to_integer(unsigned(S)));



F使用标准的数字标准执行Morten的快捷方式：F

process (Y, S) is
begin
  F <= 'X';  -- Default to avoid latch if no resulting driver in loop
  for i in 0 to 7 loop
    if S = i then
      F <= Y(i);
    end if;
  end loop;
end process;



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



F <= Y(to_integer(unsigned(S)));



process (Y, S) is
begin
  F <= 'X';  -- Default to avoid latch if no resulting driver in loop
  for i in 0 to 7 loop
    if unsigned(S) = i then
      F <= Y(i);
    end if;
  end loop;
end process;