File io 试图从Verilog写入文本文件，但输出文件为空

我需要将Verilog模块中的2个变量逐个写入一个文件。变量在单周期信号的上升沿上更新。我正在使用以下代码

integer write_file1;
integer freq_rdy_1,freq_rdy_2;

initial begin

write_file1 = $fopen("frequencies.txt","w");        
freq_rdy_1 = testbench.UUT.read_controller.freq_rdy;
freq_rdy_2 = testbench.UUT.read_controller_2.freq_rdy;
        
@(posedge freq_rdy_1)
    $fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i); 

@(posedge freq_rdy_2)  
    $fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i); 

 
#1000000
$fclose(write_file1);    
end

---

输出文本文件为空。我在这段代码中做错了什么？

问题是，只有当您看到freq_rdy_1或freq_rdy_2的posedge时，才会写入文件。但是，您永远不会得到这些信号的posedge，因为您只设置了一次（在

@posedge

语句之前）。因此，您从不向该文件写入任何内容

也许这就是你想要的：

integer write_file1;
initial begin
    write_file1 = $fopen("frequencies.txt","w");
    forever begin
        fork
            begin
                @(posedge testbench.UUT.read_controller.freq_rdy);
                $fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i);
            end
            begin
                @(posedge testbench.UUT.read_controller_2.freq_rdy);
                $fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i);
            end
            begin
                #1_000_000;
                $fclose(write_file1);
            end
        join
    end
end

---

我可以看到波形中的边缘

通过将

w

替换为

a

，即

而不是

$fopen("frequencies.txt","w");

我写

$fopen("frequencies.txt","a");

虽然每次运行模拟时都必须删除文件

其余逻辑使用

始终
块实现

initial begin 
write_file1 = $fopen("frequencies.txt","a");
end 
always @(posedge. testbench.UUT.read_controller.freq_rdy)         begin 
$fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i);
end 
always @(posedge testbench.UUT.read_controller_2.freq_rdy)       begin 
$fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i); 
end