System verilog 为什么我们可以在SystemVerilog中使用always\u ff in always\u comb？

我正在尝试创建触发器来执行移位操作，然后创建一个mux来选择我想要的正确行为。然而，SystemVerilog不允许我从顺序逻辑触发器切换到组合逻辑触发器。你有什么建议吗？谢谢

/*
    Problem 3: Consider the following design Model_1:
    a) a 8-bit input data_in [7:0]
    b) 8 register outputs data_out [7:0]
    c) Clock(CLK)
    d) a 3-bit operation code OP [2:0].
    The function of the OP code is defined as:
    000: Reset all registers to 0
    001: Arithmetic shift right (shift right and keep the highest bit value)
    010: Arithmetic shift left (shift left and fill the lowest bit with 0)
    011: Shift right (shift right lowest bit wraps to the highest bit)
    100: Shift left (shift left the highest bit wraps to the lowest bit)
    101: Keep current registers’ data
    110: Default (You can define your own logic/arithmetic operations)
    Tasks:
    Write and simulate a synthesizable 8-bit shifter register model in Systemverilog .
    */

module Model_1(output logic [7:0] data_out,input logic [7:0] data_in,input CLK,input logic [2:0] OP);
localparam zero = 0'b0;
always_comb
unique casez(OP)
3'b000: data_out = 8'b00000000;//Reset all registers to 0
3'b001: //Arithmetic shift right (shift right and keep the highest bit value)
        always_ff @(posedge CLK) data_out <= {data_in[7], data_in[7:1]}; ;
3'b010:  //Arithmetic shift left (shift left and fill the lowest bit with 0)
        always_ff @(posedge CLK) data_out <= {data_in[6:0], zero}; ;
3'b011: //Shift right (shift right lowest bit wraps to the highest bit)
        always_ff @(posedge CLK) data_out <= {data_in[0], data_in[7:1]}; ;
3'b100: //Shift left (shift left the highest bit wraps to the lowest bit)
        always_ff @(posedge CLK) data_out <= {data_in[6:0], data_in[7]}; ;
3'b101: data_out = data_in;//Keep current registers’ data
default: data_out = 8'b????????;
endcase
endmodule

---

不能使用嵌套始终块，因为它不是语言定义的一部分

verilog模块由assign语句、过程块、初始、最终以及其他模块或其他设计元素的实例组成

程序块可以包含算法代码和事件控制语句，但不能包含属于模块级的任何元素

为了表示层次结构，您可以在其他模块中实例化模块

在您的情况下，您可以在一个触发器中表达您的逻辑，如下所示：

always_ff @(posedge clk) begin
    unique casez(OP)
    3'b000: 
        data_out <= 8'b00000000;
    3'b001: 
        data_out <= {data_in[7], data_in[7:1]}; ;
    3'b010:  
        data_out <= {data_in[6:0], zero}; ;
    ...
    endcase
end 

---

你需要通过verilog教程来掌握这门语言

谢谢你的帮助！这是我的第一个SystemVerilog/Verilog类，这就是为什么我在语言方面遇到了一些问题。