Verilog HDL代码控制单元和测试台代码[端口大小不匹配]？
事实上，我检查了很多次，但我无法解决这些错误 使错误：Verilog HDL代码控制单元和测试台代码[端口大小不匹配]？,verilog,Verilog,事实上，我检查了很多次，但我无法解决这些错误 使错误： # ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (32) for port 'RF_DATA_W'. The port definition is at: control_unit.v(35). # Time: 0 ps Iteration: 0 Instance: /DA_VINCI
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (32) for port 'RF_DATA_W'. The port definition is at: control_unit.v(35).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (26) for port 'RF_ADDR_W'. The port definition is at: control_unit.v(35).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (26) for port 'RF_ADDR_R1'. The port definition is at: control_unit.v(35).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (26) for port 'RF_ADDR_R2'. The port definition is at: control_unit.v(35).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (32) for port 'ALU_OP1'. The port definition is at: control_unit.v(36).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (32) for port 'ALU_OP2'. The port definition is at: control_unit.v(36).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (6) for port 'ALU_OPRN'. The port definition is at: control_unit.v(36).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
# ** Warning: (vsim-3015) processor.v(41): [PCDPC] - Port size (1) does not match connection size (26) for port 'MEM_ADDR'. The port definition is at: control_unit.v(36).
# Time: 0 ps Iteration: 0 Instance: /DA_VINCI_TB/da_vinci_inst/processor_inst/cu_inst File: control_unit.v
`include "prj_definition.v"
module PROC_CS147_SEC05(DATA, ADDR, READ, WRITE, CLK, RST);
// output list
output [`ADDRESS_INDEX_LIMIT:0] ADDR;
output READ, WRITE;
// input list
input CLK, RST;
// inout list
inout [`DATA_INDEX_LIMIT:0] DATA;
// net section
wire [`DATA_INDEX_LIMIT:0] rf_data_w, rf_data_r1, rf_data_r2, alu_op1, alu_op2, alu_result;
wire [`ADDRESS_INDEX_LIMIT:0] rf_addr_w, rf_addr_r1, rf_addr_r2;
wire [`ALU_OPRN_INDEX_LIMIT:0] alu_oprn;
wire rf_read, rf_write;
wire zero;
// instantiation section
// Control unit
CONTROL_UNIT cu_inst (.MEM_DATA(DATA), .RF_DATA_W(rf_data_w), .RF_ADDR_W(rf_addr_w), .RF_ADDR_R1(rf_addr_r1),
.RF_ADDR_R2(rf_addr_r2), .RF_READ(rf_read), .RF_WRITE(rf_write), .ALU_OP1(alu_op1),
.ALU_OP2(alu_op2), .ALU_OPRN(alu_oprn), .MEM_ADDR(ADDR), .MEM_READ(READ),
.MEM_WRITE(WRITE), .RF_DATA_R1(rf_data_r1), .RF_DATA_R2(rf_data_r2), .ALU_RESULT(alu_result),
.ZERO(zero), .CLK(CLK), .RST(RST));
// register file
REGISTER_FILE_32x32 rf_inst (.DATA_R1(rf_data_r1), .DATA_R2(rf_data_r2), .ADDR_R1(rf_addr_r1), .ADDR_R2(rf_addr_r2),
.DATA_W(rf_data_w), .ADDR_W(rf_addr_w), .READ(rf_read), .WRITE(rf_write),
.CLK(CLK), .RST(RST));
// alu
ALU alu_inst (.OUT(alu_result), .ZERO(zero), .OP1(alu_op1), .OP2(alu_op2), .OPRN(alu_oprn));
endmodule;
`include "prj_definition.v"
module CONTROL_UNIT(MEM_DATA, RF_DATA_W, RF_ADDR_W, RF_ADDR_R1, RF_ADDR_R2, RF_READ, RF_WRITE,
ALU_OP1, ALU_OP2, ALU_OPRN, MEM_ADDR, MEM_READ, MEM_WRITE,
RF_DATA_R1, RF_DATA_R2, ALU_RESULT, ZERO, CLK, RST);
// Output signals
// Outputs for register file
output [`DATA_INDEX_LIMIT:0] RF_DATA_W;
output [`ADDRESS_INDEX_LIMIT:0] RF_ADDR_W, RF_ADDR_R1, RF_ADDR_R2;
output RF_READ, RF_WRITE;
// Outputs for ALU
output [`DATA_INDEX_LIMIT:0] ALU_OP1, ALU_OP2;
output [`ALU_OPRN_INDEX_LIMIT:0] ALU_OPRN;
// Outputs for memory
output [`ADDRESS_INDEX_LIMIT:0] MEM_ADDR;
output MEM_READ, MEM_WRITE;
// Input signals
input [`DATA_INDEX_LIMIT:0] RF_DATA_R1, RF_DATA_R2, ALU_RESULT;
input ZERO, CLK, RST;
// Inout signal
inout [`DATA_INDEX_LIMIT:0] MEM_DATA;
// State nets
wire [2:0] proc_state;
//holds program counter value, stores the current instruction, stack pointer register
reg MEM_READ, MEM_WRITE;
reg MEM_ADDR;
reg ALU_OP1, ALU_OP2;
reg ALU_OPRN;
reg RF_ADDR_W, RF_ADDR_R1, RF_ADDR_R2;
reg RF_DATA_W;
reg [1:0] state, next_state;
PROC_SM state_machine(.STATE(proc_state),.CLK(CLK),.RST(RST));
always @ (posedge CLK)
begin
if (RST)
state <= RST;
else
state <= next_state;
end
always @ (state)
begin
MEM_READ = 1'b0; MEM_WRITE = 1'b0; MEM_ADDR = 1'b0;
ALU_OP1 = 1'b0; ALU_OP2 = 1'b0; ALU_OPRN = 1'b0;
RF_ADDR_R1 = 1'b0; RF_ADDR_R2 = 1'b0; RF_ADDR_W = 1'b0; RF_DATA_W = 1'b0;
case( state )
`PROC_FETCH : begin
next_state = `PROC_DECODE;
MEM_READ = 1'b1;
RF_ADDR_R1 = 1'b0; RF_ADDR_R2 = 1'b0;
RF_ADDR_W = 1'b1;
end
`PROC_DECODE : begin
next_state = `PROC_EXE;
MEM_ADDR = 1'b1;
ALU_OP1 = 1'b1; ALU_OP2 = 1'b1; ALU_OPRN = 1'b1;
MEM_WRITE = 1'b1;
RF_ADDR_R1 = 1'b1; RF_ADDR_R2 = 1'b1;
end
`PROC_EXE : begin
next_state = `PROC_MEM;
ALU_OP1 = 1'b1; ALU_OP2 = 1'b1; ALU_OPRN = 1'b1;
RF_ADDR_R1 = 1'b0;
end
`PROC_MEM: begin
next_state = `PROC_WB;
MEM_READ = 1'b1; MEM_WRITE = 1'b0;
end
`PROC_WB: begin
next_state = `PROC_FETCH;
MEM_READ = 1'b1; MEM_WRITE = 1'b0;
end
endcase
end
endmodule;
module PROC_SM(STATE,CLK,RST);
// list of inputs
input CLK, RST;
// list of outputs
output [2:0] STATE;
// input list
input CLK, RST;
// output list
output STATE;
reg [2:0] STATE;
reg [1:0] state;
reg [1:0] next_state;
reg PC_REG, INST_REG, SP_REF;
`define PROC_FETCH 3'h0
`define PROC_DECODE 3'h1
`define PROC_EXE 3'h2
`define PROC_MEM 3'h3
`define PROC_WB 3'h4
// initiation of state
initial
begin
state = 2'bxx;
next_state = `PROC_FETCH;
end
// reset signal handling
always @ (posedge RST)
begin
state = `PROC_FETCH;
next_state = `PROC_FETCH;
end
always @ (posedge CLK)
begin
state = next_state;
end
always @(state)
begin
if (state === `PROC_FETCH)
begin
next_state = `PROC_DECODE;
print_instruction(INST_REG);
end
if (state === `PROC_DECODE)
begin
next_state = `PROC_EXE;
end
if (state === `PROC_EXE)
begin
next_state = `PROC_MEM;
print_instruction(SP_REF);
end
if (state === `PROC_MEM)
begin
next_state = `PROC_WB;
end
if (state === `PROC_WB)
begin
next_state = `PROC_FETCH;
print_instruction(PC_REG);
end
end
task print_instruction;
input [`DATA_INDEX_LIMIT:0] inst;
reg [5:0] opcode;
reg [4:0] rs;
reg [4:0] rt;
reg [4:0] rd;
reg [4:0] shamt; reg [5:0] funct; reg [15:0] immediate; reg [25:0] address;
begin
// parse the instruction
// R-type
{opcode, rs, rt, rd, shamt, funct} = inst;
// I-type
{opcode, rs, rt, immediate } = inst;
// J-type
{opcode, address} = inst;
$write("@ %6dns -> [0X%08h] ", $time, inst);
case(opcode) // R-Type
6'h00 : begin
case(funct)
6'h20: $write("add r[%02d], r[%02d], r[%02d];", rs, rt, rd);
6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rs, rt, rd);
6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rs, rt, rd);
6'h24: $write("and r[%02d], r[%02d], r[%02d];", rs, rt, rd);
6'h25: $write("or r[%02d], r[%02d], r[%02d];", rs, rt, rd);
6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rs, rt, rd);
6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rs, rt, rd);
6'h00: $write("sll r[%02d], %2d, r[%02d];", rs, shamt, rd);
6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rs, shamt, rd);
6'h08: $write("jr r[%02d];", rs);
default: $write("");
endcase
end
// I-type
6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h0f : $write("lui r[%02d], 0X%04h;", rt, immediate);
6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rs, rt, immediate);
// J-Type
6'h02 : $write("jmp 0X%07h;", address);
6'h03 : $write("jal 0X%07h;", address);
6'h1b : $write("push;");
6'h1c : $write("pop;");
default: $write("");
endcase
$write ("\n");
end
endtask
end module;
`包括“prj_definition.v”
模块控制单元（内存数据、射频数据、射频地址、射频地址R1、射频地址R2、射频读取、射频写入、，
运算单元OP1、运算单元OP2、运算单元opn、内存地址、内存读取、内存写入、，
射频数据R1、射频数据R2、ALU结果、零点、时钟、RST）；
//输出信号
//寄存器文件的输出
输出[`数据索引限制：0]射频数据；
输出[`地址索引限制：0]RF\u ADDR\u W，RF\u ADDR\u R1，RF\u ADDR\u R2；
输出射频读、射频写；
//ALU的输出
输出[`DATA_INDEX_LIMIT:0]ALU_OP1，ALU_OP2；
输出[`ALU_OPRN_INDEX_LIMIT:0]ALU_OPRN；
//存储器的输出
输出[`ADDRESS\u INDEX\u LIMIT:0]内存地址；
输出MEM_READ，MEM_WRITE；
//输入信号
输入[`DATA_INDEX_LIMIT:0]RF_DATA_R1、RF_DATA_R2、ALU结果；
输入零、时钟、RST；
//输入输出信号
inout[`DATA\u INDEX\u LIMIT:0]内存数据；
//国家网
导线[2:0]过程状态；
//保存程序计数器值，存储当前指令、堆栈指针寄存器
注册MEM_READ，MEM_WRITE；
注册会员地址；
注册ALU_OP1，ALU_OP2；
reg ALU_OPRN；
注册地址W、地址R1、地址R2；
注册射频数据；
reg[1:0]状态，下一个_状态；
进程SM状态机（.state（进程状态），.CLK（CLK），.RST（RST））；
始终@（posedge CLK）
开始
如果（RST）
状态所有地址的宽度不匹配：
- 在寄存器文件32x32中，它是
[`REG\u ADDR\u INDEX\u LIMIT:0]
- 在寄存器文件\u 32X32\u tb中，它是
[`ADDRESS\u INDEX\u LIMIT:0]
`REG\u ADDR\u INDEX\u LIMIT
！=<代码>`地址索引限制