我使用verilog进行矩阵乘法的结果未显示
我得到的矩阵乘法输出波形是十六进制的,但不是矩阵形式,如中所示 矩阵答案(我使用verilog进行矩阵乘法的结果未显示,verilog,fpga,vivado,Verilog,Fpga,Vivado,我得到的矩阵乘法输出波形是十六进制的,但不是矩阵形式,如中所示 矩阵答案(Res1)表示为{0,0},{0,0},而预期答案表示为{19,22},{43,50}。为什么我会得到这个意想不到的答案 //主文件 module mat_mul(A,B,Res); input [31:0] A; input [31:0] B; output [31:0] Res; //internal variables reg [31:0] Res; reg [7:0] A1 [0:1][0:1]; reg
Res1
)表示为{0,0},{0,0},而预期答案表示为{19,22},{43,50}。为什么我会得到这个意想不到的答案
//主文件
module mat_mul(A,B,Res);
input [31:0] A;
input [31:0] B;
output [31:0] Res;
//internal variables
reg [31:0] Res;
reg [7:0] A1 [0:1][0:1];
reg [7:0] B1 [0:1][0:1];
reg [7:0] Res1 [0:1][0:1];
integer i,j,k;
always@ (A or B)
begin
//Initialize the matrices-convert 1 D to 3D arrays
{A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
{B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
i = 0;
j = 0;
k = 0;
{Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = 32'd0;
//Matrix multiplication
for(i=0;i < 2;i=i+1)
for(j=0;j < 2;j=j+1)
for(k=0;k < 2;k=k+1)
Res1[i][j] = Res1[i][j] + (A1[i][k] * B1[k][j]);
//final output assignment - 3D array to 1D array conversion.
Res = {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]};
end
endmodule
在分配Res1和您
$display
其值之间存在竞争条件。您应该确保Res1在Res更改时更新,并且您可以在显示之前添加延迟:
always @* {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = Res;
initial begin
// Apply Inputs
A = 0; B = 0; #100;
A = {8'd1,8'd2,8'd3,8'd4};
B = {8'd5,8'd6,8'd7,8'd8};
{A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
{B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
// {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = Res;
#1; // Add some delay
$display(A1);
$display(B1);
$display(Res1);
end
@*
语法意味着每次分配的RHS(Res
)更改时,LHS(Res1
)都会更新。参考免费IEEE标准1800-2012,第9.4.2.2节隐式事件表达式列表
always @* {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = Res;
initial begin
// Apply Inputs
A = 0; B = 0; #100;
A = {8'd1,8'd2,8'd3,8'd4};
B = {8'd5,8'd6,8'd7,8'd8};
{A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
{B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
// {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = Res;
#1; // Add some delay
$display(A1);
$display(B1);
$display(Res1);
end