UART变送器计数器帮助-系统Verilog_Verilog_System Verilog

UART变送器计数器帮助-系统Verilog

verilog system-verilog

UART变送器计数器帮助-系统Verilog,verilog,system-verilog,Verilog,System Verilog,创建UART发送器时遇到了一个小问题。状态机不会超过启动状态。在使用TCL进行测试时，它保持在启动状态。代码是用一个每秒波特率为19200比特的100兆赫时钟创建的。我使用以下信息创建此代码：这是迄今为止我为本模块编写的代码： module tx( output logic Sent, output logic Sout, input wire logic clk, input wire logic Reset, input wire logic Send, input wire log

创建UART发送器时遇到了一个小问题。状态机不会超过启动状态。在使用TCL进行测试时，它保持在启动状态。代码是用一个每秒波特率为19200比特的100兆赫时钟创建的。我使用以下信息创建此代码：

这是迄今为止我为本模块编写的代码：

module tx(
output logic Sent, output logic Sout,
input wire logic clk, input wire logic Reset, input wire logic Send, input wire logic [7:0] Din);

    logic bitDone, timerDone, clrTimer, incBit, clrBit, startBit, dataBit, parityBit; logic [2:0] bitNum; logic [12:0] count;
    
    always_ff @(posedge clk)
        begin
            if (clrTimer)
            count = 0;
            if (count == 0)
                timerDone = 0;
                count <= count +1;
            if (count != 13'b1010001011001 && count != 0)
                count <= count + 1;
            else if (count == 13'b1010001011001)
                timerDone = 1;
                count <= 0;
        end
        
    always_ff @(posedge clk)
        begin
            bitDone = 0;
            if (clrBit)
                bitNum = 0;
            else if (bitNum != 3'b111 && incBit)
                bitNum <= bitNum + 1;
            else if (bitNum == 3'b111)
                bitDone = 1;               
        end
    
    typedef enum logic[2:0] {idle, start, bits, par, stop, ack, ERR='X} StateType;
    StateType ns, cs;
        
    always_comb
    begin
        ns = ERR;
        clrTimer = 0; startBit = 0; clrBit = 0; incBit = 0; dataBit = 0; parityBit = 0; Sent = 0;
        
        if (Reset)
            ns = idle;
        else
            case (cs)
                idle:
                    begin
                        clrTimer = 1;
                        if (Send)
                            ns = start;
                        else
                            ns = idle;
                    end
                start:
                    begin
                        startBit = 1;
                        if (timerDone)
                            ns = bits;
                        else
                        ns = start;
                    end
                bits:
                    begin
                        startBit = 0;
                        dataBit = 1;
                        if (!timerDone)
                            ns = bits;
                        else if (timerDone && !bitDone)
                            ns = bits;
                            incBit = 1;
                        if (timerDone && bitDone) //potential oof
                            ns = par;
                    end                
                par:
                    begin
                        dataBit = 0;
                        parityBit = 1;
                        if (timerDone)
                            ns = stop;
                        else
                            ns = par;
                    end
                stop:
                    if (timerDone)
                        ns = ack;
                    else
                        ns = stop;
                ack:
                    begin
                        Sent = 1;
                        if (Send)
                            ns = ack;
                        else
                            ns = idle;
                    end                
            endcase
                        
    end
    
    always_ff @(posedge clk)
        cs <= ns;
    
    always_ff @(posedge clk)
        if (startBit)
            Sout <= 0;
        else if (dataBit)
            Sout <= Din[bitNum];
        else if (parityBit)
            Sout <= ~^Din;
        else
            Sout <= 1;

endmodule

摆脱“启动”状态的唯一方法是使用

timerDone

。显然，你的案子从来没有设定过。很可能您的

计数有问题（如您所述）。您需要调试它并收集感兴趣信号的波形。你应该先做模拟。另一方面，请修复您的拖鞋中不正确的使用BAs（=）。
restart

add_force clk {0} {1 5} -repeat_every 10
run 10ns

add_force Reset 1
add_force Send 0
run 10ns
add_force Reset 0
run 10ns

run 50us

add_force -radix hex Din 47
add_force Send 1
run 10ns
add_force Send 0
run 1ms

add_force -radix hex Din 4F
add_force Send 1
run 10ns
add_force Send 0
run 1ms