在VHDL中将信号用作输入或输出

我写这段代码。我想在r='1'时使用数据作为输出，在w='1'时使用数据作为输入。我试过了，但没用。它有一个错误（错误：D:/modelism project/project/memory.vhd（42）：信号分配的目标不是信号）。你能帮我修一下吗

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------------------
Entity memory is
    Generic (bits: integer := 16;
         words: integer := 16);
    port (  r, w: in std_logic;-------read and write------------
        addr: in std_logic_vector(11 downto 0);
        data: inout std_logic_vector(bits-1 downto 0));

End memory;
----------------------------------------------------------------------
Architecture memory of memory is
    Type vector_array is array (0 to words-1) of std_logic_vector(bits-1 downto 0);
    constant memory: vector_array :=
                    ( "0000000000000000",
                      "0000000000000001",
                      "0000000000000010",
                      "0000000000000011",
                      "0000000000000100",
                      "0000000000000101",
                      "0000000000000110",
                      "0000000000000111",
                      "0000000000000000",
                      "0000000000000001",
                      "0000000000000010",
                      "0000000000000011",
                      "0000000000000100",
                      "0000000000000101",
                      "0000000000000110",
                      "0000000000000111");
    signal loc: integer range 0 to words - 1;
begin
    process(r, w)
    begin
        if(r = '1') then
            loc <= to_integer(signed(addr));
            data <= memory(loc);
        elsif(w = '1') then
            loc <= to_integer(signed(addr));
            memory(loc) <= data;
        end if;
    end process;
End memory;

使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
----------------------------------------------------------------------
实体内存是
通用（位：整数：=16；
字：整数：=16）；
端口（r，w:在标准逻辑中-----读写------------
地址：在标准逻辑向量中（11到0）；
数据：输入输出标准逻辑向量（位-1到0）；
终端存储器；
----------------------------------------------------------------------
内存的体系结构是
类型向量_数组是标准_逻辑_向量（位-1到0）的数组（0到字-1）；
恒定内存：矢量_数组：=
( "0000000000000000",
"0000000000000001",
"0000000000000010",
"0000000000000011",
"0000000000000100",
"0000000000000101",
"0000000000000110",
"0000000000000111",
"0000000000000000",
"0000000000000001",
"0000000000000010",
"0000000000000011",
"0000000000000100",
"0000000000000101",
"0000000000000110",
"0000000000000111");
信号位置：从0到字-1的整数范围；
开始
过程（r，w）
开始
如果（r='1'），则
loc当您声明常量时，它是一个固定值。以后不能更改它。
相反，您可以将内存声明为信号，并声明一个init常量来初始化它，如下所示：

constant init: vector_array :=
                ( "0000000000000000",
                  "0000000000000001",
                  "0000000000000010",
                  "0000000000000011",
                  "0000000000000100",
                  "0000000000000101",
                  "0000000000000110",
                  "0000000000000111",
                  "0000000000000000",
                  "0000000000000001",
                  "0000000000000010",
                  "0000000000000011",
                  "0000000000000100",
                  "0000000000000101",
                  "0000000000000110",
                  "0000000000000111");
signal memory: vector_array := init;

此外，您还需要小心使用“从inout输入”类型的端口，以便为它们指定一个值

想想当r='0'和w='0'实现“inout”管脚时会发生什么？
可以使用三态缓冲区来实现。要做到这一点，你可以不用过程来描述它，因为它与“时钟”或时间无关，而是取决于另一个信号的平稳值

大概是这样的：

当“pin_we”为“1”时，则“pin_Dout”连接到“pin_io”，否则将变为高阻抗“Z”

当你想读pin码时使用“pin码io”，当你想写pin码时使用“pin码Dout”

实体主体是
端口（引脚io:inout标准逻辑）；
端干管；
主要信息系统的架构
信号引脚：标准逻辑；
信号引脚we:std_逻辑：='0'；
开始
引脚io错误与inout无关。问题在于，您试图分配的内存是一个常量。
Entity Main is
  port (pin_io : inout std_logic);
End Main;

Architecture Behavioral of Main is
        signal  pin_Dout : std_logic;
        signal  pin_we  : std_logic := '0'; 
Begin

    pin_io <= pin_Dout when pin_we='1' else 'Z'; -- when pin_we='0';

End Behavioral;