Vhdl 使用FSM生成具有三个脉冲的波形？
嗨，我想通过FSM生成两个波形或信号（比如模式1和模式2信号），每个都有三个脉冲，比如P1、P2和P3。这些脉冲的宽度各为0.8us。 对于模式1，P1和p2相距2 us，P1和p3相距8 us（从脉冲开始） 对于模式2，P1和P2与上述相同，而P3相距21 us 1毫秒后，这些脉冲会自动重复。 我一直使用50兆赫作为我的输入时钟频率 下面是我使用FSM编写的代码Vhdl 使用FSM生成具有三个脉冲的波形？,vhdl,xilinx-ise,Vhdl,Xilinx Ise,嗨，我想通过FSM生成两个波形或信号（比如模式1和模式2信号），每个都有三个脉冲，比如P1、P2和P3。这些脉冲的宽度各为0.8us。 对于模式1，P1和p2相距2 us，P1和p3相距8 us（从脉冲开始） 对于模式2，P1和P2与上述相同，而P3相距21 us 1毫秒后，这些脉冲会自动重复。 我一直使用50兆赫作为我的输入时钟频率 下面是我使用FSM编写的代码 ------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Signal_pulse is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
modes : in STD_LOGIC_VECTOR (2 downto 0);
P_out : out STD_LOGIC);
end signal_pulse;
architecture Behavioral of signal_pulse is
type state_type is (P0, P1, P2, P3);
signal Next_state, Present_state : state_type;
signal count : integer range 0 to 100000000;
signal temp : integer range 0 to 100000000;
begin
Process(rst, clk)
begin
if(rst = '1') then
Present_state <= P0;
elsif(rising_edge(clk)) then
temp <= temp +1;
Present_state <= Next_state;
if (temp = 50000) then
temp <= 1;
end if;
--count <= count+1;
end if;
end process;
state_Process: Process(Present_state)
begin
case present_state is
when P0 =>
if (rst ='1') then
P_out <= '0';
count <= 0;
next_state <= P0;
else
count <= 0;
next_state <= P1;
end if;
when P1 =>
if(modes = "001") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
elsif (modes = "010") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
else
P_out <= '0';
end if;
when P2 =>
if(modes = "001") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 400) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 400) then
next_state <= P3;
end if;
elsif (modes = "010") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 1050) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 1050) then
next_state <= P3;
end if;
else
P_out <= '0';
end if;
when P3 =>
if(modes = "001") then
if (count < 440) then
count <= count +1;
P_out <= '1';
next_state <= p3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
elsif(Modes = "010") then
if (count < 1090) then
count <= count +1;
P_out <= '1';
next_state <= P3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
else
P_out <= '0';
end if;
end case;
end Process;
end Behavioral;
-----------------------------------------------------------------------------
图书馆IEEE；
使用IEEE.STD_LOGIC_1164.ALL；
实体信号_脉冲为
端口（时钟：在标准逻辑中；
rst：标准逻辑中；
模式：标准逻辑向量（2到0）；
P_out：输出标准逻辑）；
脉冲结束信号；
脉冲信号的结构是
类型状态_类型为（P0、P1、P2、P3）；
信号下一个状态、当前状态：状态类型；
信号计数：整数范围0到100000000；
信号温度：整数范围0至100000000；
开始
过程（rst、clk）
开始
如果（rst='1'），则
当前状态我在您的HDL中做了一些修改，将两个进程FSM更改为单个进程，状态和输出现在实际上正在更改，
虽然书籍和文献使用两个过程，但现在许多专业人士和非官方标准建议使用单一过程，尽管有很大的讨论和争论来决定哪个更好，我觉得没有太大的区别，虽然在使用两个或三个过程时，您必须注意组合过程的敏感性列表，但不完整的过程可能会导致组合过程中出现问题，就像您所面临的问题一样，对于初学者，我建议使用单一过程，除非您完全确定自己正在做什么
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Signal_pulse is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
modes : in STD_LOGIC_VECTOR (2 downto 0);
P_out : out STD_LOGIC);
end signal_pulse;
architecture Behavioral of signal_pulse is
type state_type is (P0, P1, P2, P3);
signal Next_state, Present_state : state_type;
signal count : integer range 0 to 100000000;
signal temp : integer range 0 to 100000000;
begin
Process(rst, clk)
begin
if(rst = '1') then
Present_state <= P0;
elsif(rising_edge(clk)) then
temp <= temp +1;
Present_state <= Next_state;
if (temp = 50000) then
temp <= 1;
end if;
--count <= count+1;
case present_state is
when P0 =>
if (rst ='1') then
P_out <= '0';
count <= 0;
next_state <= P0;
else
count <= 0;
next_state <= P1;
end if;
when P1 =>
if(modes = "001") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
elsif (modes = "010") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
else
P_out <= '0';
end if;
when P2 =>
if(modes = "001") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 400) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 400) then
next_state <= P3;
end if;
elsif (modes = "010") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 1050) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 1050) then
next_state <= P3;
end if;
else
P_out <= '0';
end if;
when P3 =>
if(modes = "001") then
if (count < 440) then
count <= count +1;
P_out <= '1';
next_state <= p3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
elsif(Modes = "010") then
if (count < 1090) then
count <= count +1;
P_out <= '1';
next_state <= P3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
else
P_out <= '0';
end if;
end case;
end if;
end Process;
end Behavioral;
IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
实体信号_脉冲为
端口（时钟：在标准逻辑中；
rst：标准逻辑中；
模式：标准逻辑向量（2到0）；
P_out：输出标准逻辑）；
脉冲结束信号；
脉冲信号的结构是
类型状态_类型为（P0、P1、P2、P3）；
信号下一个状态、当前状态：状态类型；
信号计数：整数范围0到100000000；
信号温度：整数范围0至100000000；
开始
过程（rst、clk）
开始
如果（rst='1'），则
当前状态我在您的HDL中做了一些修改，将两个进程FSM更改为单个进程，状态和输出现在实际上正在更改，
虽然书籍和文献使用两个过程，但现在许多专业人士和非官方标准建议使用单一过程，尽管有很大的讨论和争论来决定哪个更好，我觉得没有太大的区别，虽然在使用两个或三个过程时，您必须注意组合过程的敏感性列表，但不完整的过程可能会导致组合过程中出现问题，就像您所面临的问题一样，对于初学者，我建议使用单一过程，除非您完全确定自己正在做什么
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Signal_pulse is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
modes : in STD_LOGIC_VECTOR (2 downto 0);
P_out : out STD_LOGIC);
end signal_pulse;
architecture Behavioral of signal_pulse is
type state_type is (P0, P1, P2, P3);
signal Next_state, Present_state : state_type;
signal count : integer range 0 to 100000000;
signal temp : integer range 0 to 100000000;
begin
Process(rst, clk)
begin
if(rst = '1') then
Present_state <= P0;
elsif(rising_edge(clk)) then
temp <= temp +1;
Present_state <= Next_state;
if (temp = 50000) then
temp <= 1;
end if;
--count <= count+1;
case present_state is
when P0 =>
if (rst ='1') then
P_out <= '0';
count <= 0;
next_state <= P0;
else
count <= 0;
next_state <= P1;
end if;
when P1 =>
if(modes = "001") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
elsif (modes = "010") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
else
P_out <= '0';
end if;
when P2 =>
if(modes = "001") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 400) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 400) then
next_state <= P3;
end if;
elsif (modes = "010") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 1050) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 1050) then
next_state <= P3;
end if;
else
P_out <= '0';
end if;
when P3 =>
if(modes = "001") then
if (count < 440) then
count <= count +1;
P_out <= '1';
next_state <= p3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
elsif(Modes = "010") then
if (count < 1090) then
count <= count +1;
P_out <= '1';
next_state <= P3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
else
P_out <= '0';
end if;
end case;
end if;
end Process;
end Behavioral;
IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
实体信号_脉冲为
端口（时钟：在标准逻辑中；
rst：标准逻辑中；
模式：标准逻辑向量（2到0）；
P_out：输出标准逻辑）；
脉冲结束信号；
脉冲信号的结构是
类型状态_类型为（P0、P1、P2、P3）；
信号下一个状态、当前状态：状态类型；
信号计数：整数范围0到100000000；
信号温度：整数范围0至100000000；
开始
过程（rst、clk）
开始
如果（rst='1'），则
表示感谢，但我没有得到想要的结果。在将温度添加到第二个过程的灵敏度列表中后，我也开始获得脉冲，但所需的信号仍然很遥远。我忘了提到我还没有检查功能，你能告诉我们你现在得到的波形吗？为了更清楚，我添加了一个答案，请看一看谢谢，但我没有得到想要的输出。在将温度添加到第二个过程的灵敏度列表中后，我也开始获得脉冲，但所需的信号仍然很遥远。我忘了提到我还没有检查功能，你能告诉我们你现在得到的波形吗？为了更清楚，我补充了一个答案，请看一看