Vhdl 如何为我的fpga创建时钟信号

我的问题很简单，因为我在Xilinx sp605板上有一个200MHZ的时钟，因为我的设计只能在100Mhz上运行，所以我希望输入时钟为100Mhz，所以要实现这一点：我是否只需要在UCF文件中写入时钟值，就这样 我必须创建一个需要200Mhz的VHDL组件，并将其设置为100Mhz

以下是mu ucf文件：

#  Spartan-6 SP605 Evaluation Platform
Net fpga_0_RS232_Uart_1_RX_pin LOC = H17  |IOSTANDARD=LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin LOC = B21  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<0> LOC=C18  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<1> LOC=Y6  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<2> LOC=W6  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<3> LOC=E4  |IOSTANDARD=LVCMOS15;
NET LED<0> LOC = "D17"; ## 2 on DS3 LED
NET LED<1> LOC = "AB4"; ## 2 on DS4 LED
NET LED<2> LOC = "D21"; ## 2 on DS5 LED
NET LED<3> LOC = "W15"; ## 2 on DS6 LED
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=L20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=P20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=N15  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=T22  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=P19  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=Y22  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=Y21  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=W22  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=M16  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J22  |IOSTANDARD = LVCMOS25  |TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=T8  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=U10  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T10  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AB8  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AA8  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDC_pin LOC=R19  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDIO_pin LOC=V20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_MDINT_pin LOC=J20  |IOSTANDARD = LVCMOS25  |TIG;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_we_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cke_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<13> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<14> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<15> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ldm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_odt_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_rzq_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_zio_pin IOSTANDARD = SSTL15_II;
Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Net fpga_0_clk_1_sys_clk_p_pin LOC = K21  |IOSTANDARD=LVDS_25  |DIFF_TERM = TRUE;
Net fpga_0_clk_1_sys_clk_n_pin LOC = K22  |IOSTANDARD=LVDS_25  |DIFF_TERM = TRUE;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = H8  |IOSTANDARD=LVCMOS15  |PULLUP  |TIG;

#斯巴达-6 SP605评估平台
净fpga_0_RS232_Uart_1_RX_引脚LOC=H17 | IOSTANDARD=LVCMOS25；
Net fpga_0_RS232_Uart_1_TX_引脚LOC=B21 | IOSTANDARD=LVCMOS25；
Net fpga_0_DIP_开关_4位_GPIO_IO_引脚LOC=C18 | IOSTANDARD=LVCMOS25；
Net fpga_0_DIP_开关_4位_GPIO_IO_引脚LOC=Y6 | IOSTANDARD=LVCMOS25；
Net fpga_0_DIP_开关_4位_GPIO_IO_引脚LOC=W6 | IOSTANDARD=LVCMOS25；
Net fpga_0_DIP_开关_4位_GPIO_IO_引脚LOC=E4 | IOSTANDARD=LVCMOS15；
净发光二极管LOC=“D17”#DS3上的2个LED
净发光二极管LOC=“AB4”#DS4上的2个LED
净发光二极管LOC=“D21”#DS5上的2个LED
净发光二极管LOC=“W15”#DS6上的2个LED
Net fpga_0_以太网_MAC_PHY_tx_clk_引脚LOC=L20 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_rx_clk_引脚LOC=P20 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_crs_引脚LOC=N15 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_dv_引脚LOC=T22 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_物理_rx_数据_引脚LOC=P19 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_物理_rx_数据_引脚LOC=Y22 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_物理_rx_数据_引脚LOC=Y21 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_物理_rx_数据_引脚LOC=W22 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_col_引脚LOC=M16 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_rx_er_引脚LOC=U20 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_rst_n_引脚LOC=J22 | IOSTANDARD=LVCMOS25 | TIG；
Net fpga_0_Ethernet_MAC_PHY_tx_en_引脚LOC=T8 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_tx_数据_引脚LOC=U10 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_tx_数据_引脚LOC=T10 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_tx_数据_引脚LOC=AB8 | IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_PHY_tx_数据_引脚LOC=AA8 | IOSTANDARD=LVCMOS25；
Net fpga 0以太网MAC物理MDC引脚LOC=R19 IOSTANDARD=LVCMOS25；
Net fpga 0以太网MAC物理MDIO引脚LOC=V20 IOSTANDARD=LVCMOS25；
Net fpga_0_以太网_MAC_MDINT_引脚LOC=J20 | IOSTANDARD=LVCMOS25 | TIG；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_addr_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_ba_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_ba_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_ba_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_ras_n_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_we_n_pin IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_cke_pin IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_clk_引脚IOSTANDARD=DIFF_SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin IOSTANDARD=DIFF_SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_引脚IOSTANDARD=DIFF_SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin IOSTANDARD=DIFF_SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_引脚IOSTANDARD=DIFF_SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin IOSTANDARD=DIFF_SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_udm_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_ldm_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_odt_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_mcbx_dram_DDR3_rst_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_rzq_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_MCB_DDR3_zio_引脚IOSTANDARD=SSTL15_II；
Net fpga_0_clk_1_sys_clk_p_pin TNM_Net=sys_clk_pin；
TIMESPEC TS_sys_clk_pin=周期sys_clk_pin 200000 kHz；
净fpga 0时钟1系统时钟p引脚LOC=K21 | IOSTANDARD=LVDS | 25 |差异项=TRUE；
净fpga 0时钟1系统时钟n引脚LOC=K22 | IOSTANDARD=LVDS | 25 |差异项=TRUE；
Net fpga_0_rst_1_系统_rst_引脚TIG；
净fpga_0_rst_1_sys_rst_pin LOC=H8 | IOSTANDARD=LVCMOS15 | PULLUP | TIG；

LOC K21和k22已由microblaze拍摄，我无法使用它们，问题是即使在文档中我也无法获得全局时钟引脚和它们的频率（顺便说一句，我指的是此文档（），还有为什么EDK ucf文件不符合