如何使这个MOD-5计数器工作（vhdl）？

我正在尝试用VHDL实现MOD-5计数器，并尝试使用以下步骤：

• 我创建了一个

  GENERIC

  N位计数器
• 然后我实例化了一个3位计数器
• 使用3位计数器作为

  组件

  我在达到4时将计数重置为0

我已经测试过了，但它不工作，在整个模拟过程中，计数信号保持未定义状态。谁能解决这个问题

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY counter_n_bit IS
GENERIC(
    N : INTEGER);
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    -- Clear is a synchronous reset
    Clear : IN STD_LOGIC;
    Count : BUFFER UNSIGNED(N - 1 DOWNTO 0)
    );
END counter_n_bit;

ARCHITECTURE behaviour OF counter_n_bit IS

BEGIN

    PROCESS(Clock)
    BEGIN
        -- since this is a synchronous circuit, signal should
        -- only change on clock's edges. I chose rising edges.
        IF Clock'EVENT AND Clock = '1' THEN
            -- if clear is set to 1, no matter the other signals, the counter resets
            -- same if it got to the max integer that can be represented on N bits (2^N - 1)
            IF Clear = '1' OR Count = 2**N - 1 THEN
                Count <= (OTHERS => '0');
            ELSE
            -- if none of this condtions are satisfied we're in the regular case
            -- and I update the Count value incrementing it by one
                IF Enable = '1' THEN
                    Count <= Count + 1;
                END IF;
            END IF;
        END IF;
    END PROCESS;

END behaviour;

IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
使用IEEE.NUMERIC_STD.ALL；
实体计数器_3_位_5为
港口(
时钟：标准逻辑；
启用：在STD_逻辑中；
清除：在标准逻辑中；
计数：缓冲区未签名（2到0）
);
结束计数器3位5；
计数器_3_位_5的架构行为为
元件计数器3位
港口(
时钟：标准逻辑；
启用：在STD_逻辑中；
清除：在标准逻辑中；
计数：输出未签名（2到0）
);
端部元件；
开始
--3位计数器的实例化
计数器\u 3：计数器\u 3 \u位端口映射（时钟=>时钟，启用=>启用，清除=>清除，计数=>计数）；
进程（计数）
开始
如果Count=“100”，则
计数“…计数信号在整个模拟中保持未定义。”在计数器_3_位_5中，有两个用于计数的驱动器，计数器_3的计数输出和未标记的进程计数分配。Count的值将是这两个的分辨率。可能还有更多的问题，您的代码对于这个问题来说不是最小的。我如何改进它？我应该删除计数器3位并直接将计数器3位设置为计数器5位吗？所有要计数的赋值都应该在一个过程中完成。好的！我现在正在试。如果我有其他问题，我会更新这个问题。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY counter_3_bit IS
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : OUT UNSIGNED(2 DOWNTO 0)
    );
END counter_3_bit;

ARCHITECTURE behaviour OF counter_3_bit IS

COMPONENT counter_n_bit 
GENERIC(
    N : INTEGER);
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : OUT UNSIGNED(N - 1 DOWNTO 0)
    );
END COMPONENT;

BEGIN
    -- instantiation of a 3 bit counter
    counter_3: counter_n_bit GENERIC MAP (N => 3) PORT MAP (Clock => Clock, Enable => Enable, Clear => Clear, Count => Count);

END behaviour;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY counter_3_bit_5 IS
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : BUFFER UNSIGNED(2 DOWNTO 0)
    );
END counter_3_bit_5;

ARCHITECTURE behaviour OF counter_3_bit_5 IS

COMPONENT counter_3_bit 
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : OUT UNSIGNED(2 DOWNTO 0)
    );
END COMPONENT;

BEGIN
    -- instantiation of a 3 bit counter
    counter_3: counter_3_bit PORT MAP (Clock => Clock, Enable => Enable, Clear => Clear, Count => Count);
    
    PROCESS (Count)
    
    BEGIN

        IF Count = "100" THEN
            Count <= "000";
        END IF;

    END PROCESS;


END behaviour;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY tb_counter_3_bit_5 IS
END tb_counter_3_bit_5;

ARCHITECTURE behaviour OF tb_counter_3_bit_5 IS

COMPONENT counter_3_bit_5 
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : BUFFER UNSIGNED(2 DOWNTO 0)
    );
END COMPONENT;

SIGNAL Clock_tb, Clear_tb, Enable_tb : STD_LOGIC;
SIGNAL Count_tb : UNSIGNED(2 DOWNTO 0);

BEGIN

    Clear_tb <= '1', '0' AFTER 6 ns;
    Enable_tb <= '1';

    clk_process: PROCESS
    BEGIN
        Clock_tb <= '0';
        WAIT FOR 5 ns;
        Clock_tb <= NOT Clock_tb;
        WAIT FOR 5 ns;
    END PROCESS;
    -- instantiation of a 3 bit counter
    dut: counter_3_bit_5 PORT MAP (Clock => Clock_tb, Enable => Enable_tb, Clear => Clear_tb, Count => Count_tb);

END behaviour;