VHDL，Spartan-3AN输出

我的设计基本上是一个多功能日历，具有以下特点：

以[年/月/日：小时：分钟：秒]格式显示日期 秒表。 惊恐 当报警激活时，可以使用Snooz选项，您可以更改Snooz周期或停止报警。 事件，保存在选定的日期和时间，并在事件发生时启用报警。 这就是我计算时钟[小时：分钟：秒]的方法

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Clock is
port (clk : in std_logic;
      seconds : out integer ;
      minutes : out integer;
      hours : out integer
     );
end Clock;

architecture Behavioral of Clock is
        signal sec,min : integer range 0 to 60 := 0 ;
        signal hour : integer range 0 to 24 := 0 ;
begin
        seconds <= sec;
        minutes <= min;
        hours <= hour;

        process (clk)
        begin
            if (clk'event and clk='1') then
                sec <=sec+1 ;
                if (sec=60) then 
                    min <= min+1 ;
                    sec <= 0 ;
                    if (min=60) then 
                        hour <= hour +1;
                        min<=0;
                        if ( hour = 24) then
                            hour <= 0;
                        end if;
                    end if ;
                end if;
            end if;
        end process ;

end Behavioral;

而这段代码做的休息日期信息[年/月/日]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity calender is
   port (
        clk : in std_logic;
      LYear     : in  std_logic;
      O_DAYS_IN_MONTH : out unsigned(4 downto 0)
      );
end entity calender;

architecture Behavioral of calender is

    signal hours :integer;
    signal Mday,day : integer range 1 to 31:=1;
    signal month: integer range 1 to 12:=1;
    signal year : integer range 2010 to 2030 :=2010;

begin
    u0 : entity work.Clock port map ( clk => clk , hours => hours );

    process ( clk,hours )
    begin 
        if (clk'event and clk='1') then
            if ( hours = 23 ) then 
                day <= day +1 ;
                if ( day = Mday ) then 
                    day <= 1;
                    month <= month +1 ;
                    if ( month = 13 ) then 
                        month <= 1 ;
                        year <= year +1;
                        if ( year = 2030 ) then 
                            year <= 2010;
                        end if;
                    end if;
                end if;
            end if;
        end if;
    end process;

    process ( month , LYear)
    begin
        if ( month = 9  or month = 4 or month = 6 or  month = 11) then 
            Mday <= 30;
        elsif ( month = 2 and LYear = '0') then 
            Mday <= 28 ;
        elsif ( month = 2 and LYear = '1') then 
            Mday <= 29;
        else 
            Mday <= 31;
        end if;
    end process;

   O_DAYS_IN_MONTH <= to_unsigned( Mday ,O_DAYS_IN_MONTH'length) ;                   

end architecture Behavioral;

我还为秒表单独编码，它在斯巴达3中的7段上显示，如下所示

library IEEE;                                                       
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity stop_watch is
port(
        clr: in std_logic;
        strt: in std_logic;
        clk : in std_logic;
        anode : out std_logic_vector (3 downto 0);
        seg : out std_logic_vector (7 downto 0)
        ); 
end stop_watch ;

architecture Behavioral of stop_watch is
    signal dig1,dig2,dig3,dig4:std_logic_vector (7 downto 0);
    signal clk10hz,clk1khz:std_logic;
begin


    process (clr,strt,clk10hz)
        variable d1,d2,d4:integer range 0 to 10;
        variable d3:integer range 0 to 6;
     begin
        if(clr='1')then
            d1:=0;
            d2:=0;
            d3:=0;
            d4:=0;
        elsif(clk10hz'event and clk10hz='1') then
            if(strt='0')then
                d1:=d1;
                d2:=d2;
                d3:=d3;
                d4:=d4;
            else
                d1:= d1+1;
                if(d1=10)then
                    d1:=0;
                    d2:=d2+1;
                end if;
                if(d2=10)then
                    d3:=d3+1;
                    d2:=0;
                end if;
                if(d3=6)then
                    d4:=d4+1;
                    d3:=0;
                end if; 
                if(d4=10)then
                    d4:=0;
                end if;
            end if;
        end if; 


        case d1 is 
            when 0 => dig1 <="10000001";
            when 1 => dig1 <="11001111";
            when 2 => dig1 <="10010010";
            when 3 => dig1 <="10000110";
            when 4 => dig1 <="11001100";
            when 5 => dig1 <="10100100";
            when 6 => dig1 <="10100000";
            when 7 => dig1 <="10001111";
            when 8 => dig1 <="10000000";
            when 9 => dig1 <="10001100";
            when 10 => dig1 <="10000001";
        end case;

        case d2 is
            when 0 => dig2 <="00000001";
            when 1 => dig2 <="01001111";
            when 2 => dig2 <="00010010";
            when 3 => dig2 <="00000110";
            when 4 => dig2 <="01001100";
            when 5 => dig2 <="00100100";
            when 6 => dig2 <="00100000";
            when 7 => dig2 <="00001111";
            when 8 => dig2 <="00000000";
            when 9 => dig2 <="00001100";
            when 10 => dig2 <="00000001";
        end case;

        case d3 is 
            when 0 => dig3 <="10000001";
            when 1 => dig3 <="11001111";
            when 2 => dig3 <="10010010";
            when 3 => dig3 <="10000110";
            when 4 => dig3 <="11001100";
            when 5 => dig3 <="10100100";
            when 6 => dig3 <="10100000";
        end case;

        case d4 is
            when 0 => dig4 <="00000001";
            when 1 => dig4 <="01001111";
            when 2 => dig4 <="00010010";
            when 3 => dig4 <="00000110";
            when 4 => dig4 <="01001100";
            when 5 => dig4 <="00100100";
            when 6 => dig4 <="00100000";
            when 7 => dig4 <="00001111";
            when 8 => dig4 <="00000000";
            when 9 => dig4 <="00001100";
            when 10 => dig4 <="00000001";
        end case;
    end process;


    process (clk)
        Variable Count: integer range 0 to 5000000 :=0;
    begin
        if (Clk'event and Clk ='1') then
            count := count+1;
            if ( count < 2500000 ) then
                clk10Hz <= '0';
            elsif (count = 2500000) then
                clk10Hz <= '1';
            elsif (count = 5000000) then
                clk10Hz <= '0' ; count := 0;
            end if; 
        end if;
    end process ;


    process (clk1Khz)
        variable cnt : integer range 0 to 3:= 0;
    begin
        if (clk1Khz'event and clk1Khz='1') then
            case cnt is
                when 0 => anode <="1110";
                    seg<= dig1;
                    cnt:=cnt+1;
                when 1 => anode <="1101";
                    seg<= dig2;
                    cnt:=cnt+1;
                when 2 => anode <="1011";
                    seg<= dig3;
                    cnt:=cnt+1;
                when 3 => anode <="0111";
                    seg <= dig4;
                    cnt:=0;
                end case;
        end if;
   end process;


    process (clk)
        Variable Count: integer range 0 to 50000 :=0;
    begin
        if (Clk'event and Clk ='1') then
            count := count+1;
            if ( count < 25000 ) then
                clk1Khz <= '0';
            elsif (count = 25000) then
                clk1Khz <= '1';
            elsif (count = 50000) then
                clk1Khz <= '0' ; count := 0;
            end if; 
        end if;
    end process ;


end     Behavioral; 

现在，我的问题是

我应该把所有这些信息都放在斯巴达3-AN的LCD显示屏上，我完全没有这方面的经验，我知道我的代码还没有完成，还需要像秒表代码那样进行一些时钟分割，我知道当与LCD交互时，时钟划分会发生变化，所以我现在就不用麻烦在我的代码编写中编写了。 如果有人能给我一些关于如何处理LCD显示器的信息，如何显示字符，如何从一个字符移动到另一个字符，这样我就可以在键盘上发生事件时更改它

---

你可以说，我在Spartan 3AN中处理液晶显示器方面没有经验，我曾尝试查看xilinx提供的电路板，我从中了解了一些东西，但仍然不知道如何使用它，如果有任何教程可以帮助我，那就足够了。

用户指南或多或少地包含了您所需要的一切。试着再读一遍，然后开始尝试。如果你需要更多的界面信息，试着在谷歌上搜索HD44780，这是一种相当的、非常常见的LCD控制器芯片。你不需要重新发明轮子。例如，opencores列出了几个LCD控制器，如sonicwave。。。好吧，那我再给它一次机会，如果再也没有机会的话，我会去找你说的那个搜索，谢谢你，伙计。佩培尔。。。它要求我进行需要验证的登录，这将需要1-2天的时间：/，但感谢mate在验证后查看它o/如果您查看标题为Stackoverflow的问题，这里提供了一个几乎可以正常工作的驱动程序的代码。Galland的回答及其评论解释了需要纠正的地方。这是通过使用[vhdl]lcd搜索stackoverflow发现的，共有28个结果，在找到它之前，我扫描了3/4。opencores控制器使用128位std_逻辑_向量作为行缓冲区，而链接SO问题只是写入序列字符。