VHDL：交通灯状态机未合成
所以我正在创建一个红绿灯状态机，我的代码合成有几个问题。我一直在努力解决这个问题 问题：VHDL：交通灯状态机未合成,vhdl,xilinx,Vhdl,Xilinx,所以我正在创建一个红绿灯状态机，我的代码合成有几个问题。我一直在努力解决这个问题 问题： 计数器模块未与其他模块连接 顶层示意图：可在 顶级.vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevel is Port ( MasterReset : in STD_LOGIC; Cloc
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopLevel is Port ( MasterReset : in STD_LOGIC;
Clock : in STD_LOGIC;
CarEW : in STD_LOGIC;
CarNS : in STD_LOGIC;
PedEW : in STD_LOGIC;
PedNS : in STD_LOGIC;
debugLED : out STD_LOGIC;
Lights : out STD_LOGIC_VECTOR (3 downto 0));
end TopLevel;
architecture Behavioral of TopLevel is
-- Synchronized Button inputs --
signal PedEWButton : STD_LOGIC;
signal PedNSButton : STD_LOGIC;
signal CarEWButton : STD_LOGIC;
signal CarNSButton : STD_LOGIC;
--Reset, Clear and Count Signals --
signal ClearRegister : STD_LOGIC;
signal ResetCounter : STD_LOGIC;
signal Count: STD_LOGIC_VECTOR (8 downto 0);
-- Registered Ped Signals --
signal PedEWReg : STD_LOGIC;
signal PedNSReg : STD_LOGIC;
begin
-- Check For MasterReset and Sync Inputs
process (MasterReset, clock, CarEWButton, CarNSButton, PedEWButton, PedNSButton)
begin
if (MasterReset = '1') then
debugLED <= '1';
CarNSButton <= '1';
CarEWButton <= '1';
PedEWButton <= '1';
PedNSButton <= '1';
elsif rising_edge(clock) then
CarEWButton <= CarEW;
CarNSButton <= CarNS;
PedEWButton <= PedEW;
PedNSButton <= PedNS;
end if;
end process;
-- Instantiate State Machine --
StateMachine:
entity work.TrafficStatesMachine
Port Map (
MasterReset => MasterReset,
Clock => Clock,
CarEWButton => CarEWButton,
CarNSButton => CarNSButton,
PedEWButton => PedEWReg,
PedNSButton => PedNSReg,
Counter => Count,
Lights => Lights,
ResetCounter => ResetCounter,
ClearRegister => ClearRegister
);
-- Instantiate Counter --
Counter:
entity work.Counter
Port Map (
MasterReset => MasterReset,
ResetCounter => ResetCounter,
Clock => Clock,
Counter => Count
);
-- Instantiate PedRegister --
PedRegister:
entity work.PedRegister
Port Map (
PedNSButton => PedNSButton,
PedEWButton => PedEWButton,
PedNSRegOut => PedNSReg,
PedEWRegOut => PedEWReg,
ClearRegister => ClearRegister
);
end architecture Behavioral;
--===================================================================
-- Traffic states Machine
--
-- A states Machine to interpret and manage traffic
--
--===================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TrafficStatesMachine is
Port (
MasterReset : IN std_logic;
Clock : IN std_logic;
CarEWButton : IN std_logic;
CarNSButton : IN std_logic;
PedEWButton : IN std_logic;
PedNSButton : IN std_logic;
Counter : IN std_logic_vector(8 downto 0);
ResetCounter : OUT std_logic;
ClearRegister : OUT std_logic;
Lights : OUT std_logic_vector(3 downto 0)
);
end TrafficStatesMachine;
architecture Behavioural of TrafficStatesMachine is
type states_type is (EWCarGreen, EWPedGreen, EWAmber, NSCarGreen, NSPedGreen, NSAmber );
signal states: states_type;
begin
process( MasterReset, Clock, CarEWButton, CarNSButton, PedEWButton, PedNSButton, Counter )
begin
if (MasterReset = '1') then
states <= EWCarGreen;
elsif rising_edge(clock) then
case states is
when EWCarGreen =>
ClearRegister <= '0';
if (Counter < "111111111") then
if (PedEWButton = '1') then
if (CarNSButton = '0') and (PedNSButton = '0') then
states <= EWPedGreen;
ResetCounter <= '1';
else
states <= EWCarGreen;
end if;
end if;
elsif (Counter = "111111111") then
if (CarNSButton = '1') then
states <= EWAmber;
ResetCounter <= '1';
elsif (PedNSButton = '1') then
states <= EWAmber;
ResetCounter <= '1';
else
states <= EWCarGreen;
end if;
end if;
when EWPedGreen =>
ClearRegister <= '1';
ResetCounter <= '0';
if (Counter = "110010000") then
states <= EWCarGreen;
else
states <= EWPedGreen;
end if;
when EWAmber =>
ResetCounter <= '0';
if (Counter = "011001000") then
if (PedNSButton = '1') then
states <= NSPedGreen;
ResetCounter <= '1';
else
states <= NSCarGreen;
ResetCounter <= '1';
end if;
else
states <= EWAmber;
end if;
when NSCarGreen =>
ResetCounter <= '0';
ClearRegister <= '0';
if (Counter < "111111111") then
if (PedNSButton = '1') then
if (CarEWButton = '0') and (PedEWButton = '0') then
states <= NSPedGreen;
ResetCounter <= '1';
else
states <= NSCarGreen;
end if;
end if;
elsif (Counter = "111111111") then
if (CarEWButton = '1') then
states <= NSAmber;
ResetCounter <= '1';
elsif (PedEWButton = '1') then
states <= NSAmber;
ResetCounter <= '1';
else
states <= NSCarGreen;
end if;
end if;
when NSPedGreen =>
ResetCounter <= '0';
ClearRegister <= '1';
if (Counter = "110010000") then
states <= NSCarGreen;
else
states <= NSPedGreen;
end if;
when NSAmber =>
ResetCounter <= '0';
if (Counter = "011001000") then
if (PedEWButton = '1') then
states <= EWPedGreen;
ResetCounter <= '1';
else
states <= EWCarGreen;
ResetCounter <= '1';
end if;
else
states <= NSAmber;
end if;
end case;
end if;
end process;
process( states )
begin
case states is
when EWCarGreen => lights <= "0010";
when EWPedGreen => lights <= "0011";
when EWAmber => lights <= "0001";
when NSCarGreen => lights <= "1000";
when NSPedGreen => lights <= "1100";
when NSAmber => lights <= "0100";
when others => lights <= "0010";
end case;
end process;
end Behavioural;
--===================================================================
-- Counter.vhdl
-- A counter to give time delays
--===================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port ( MasterReset : in std_logic;
Clock : in std_logic;
ResetCounter : in std_logic;
Counter : out std_logic_vector(8 downto 0));
end entity Counter;
architecture Behavioural of Counter is
signal Count : std_logic_vector(8 downto 0);
begin
Counter <= Count;
-- Produce Count sequence from 0 ... 512
process( MasterReset, Clock, ResetCounter)
begin
if (MasterReset = '1') then
Count <= "000000000"; -- start count from 0
elsif rising_edge(clock) then
if (ResetCounter = '1') then
Count <= "000000000";
elsif (Count < "111111111") then
Count <= Count + "000000001";
else
Count <= "111111111";
end if;
end if;
end process;
end architecture Behavioural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PedRegister is
Port ( ClearRegister : in STD_LOGIC;
PedNSButton: in STD_LOGIC;
PedEWButton : in STD_LOGIC;
PedNSRegOut : out STD_LOGIC;
PedEWRegOut : out STD_LOGIC);
end PedRegister;
architecture Behavioral of PedRegister is
signal PedNSReg : STD_LOGIC;
signal PedEWReg : STD_LOGIC;
begin
PedNSRegOut <= PedNSReg;
PedEWRegOut <= PedEWReg;
process (PedNSButton, PedEWButton, ClearRegister)
begin
if ClearRegister = '1' then
PedNSReg <='0';
elsif PedNSButton = '1' then
PedNSReg <='1';
else
PedNSReg <= '0';
end if;
if ClearRegister = '1' then
PedEWReg <= '0';
elsif PedEWButton = '1' then
PedEWReg <='1';
else
PedEWReg <= '0';
end if;
end process;
end Behavioral;
IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
使用IEEE.STD_LOGIC_ARITH.ALL；
使用IEEE.STD_LOGIC_UNSIGNED.ALL；
实体顶层为端口（主复位：在标准逻辑中；
时钟：标准逻辑；
CarEW：标准逻辑；
CarNS：标准逻辑；
PedEW：标准逻辑；
PedNS：标准逻辑；
调试：输出标准逻辑；
灯：断开标准逻辑向量（3到0）；
末端顶层；
顶层的架构行为是
--同步按钮输入--
信号按钮：标准逻辑；
信号按钮：标准逻辑；
信号CAREWBUTON：标准逻辑；
信号按钮：标准逻辑；
--复位、清除和计数信号--
信号清除寄存器：标准逻辑；
信号复位计数器：标准逻辑；
信号计数：标准逻辑向量（8到0）；
--注册Ped信号--
信号灯：标准逻辑；
信号PedNSReg:STD_逻辑；
开始
--检查主复位和同步输入
过程（主复位、时钟、CarEWButton、CarNSButton、PedwButton、PedNSButton）
开始
如果（主复位='1'），则
调试重置计数器，
ClearRegister=>ClearRegister
);
--实例化计数器--
柜台：
实体工作。柜台
港口地图(
MasterReset=>MasterReset，
ResetCounter=>ResetCounter，
时钟=>时钟，
计数器=>计数
);
--实例化寄存器--
登记册：
实体工作注册
港口地图(
PedNSButton=>PedNSButton，
PedEWButton=>PedEWButton，
PedNSRegOut=>PedNSReg，
Pederwegout=>Pederweg，
ClearRegister=>ClearRegister
);
终端架构行为；
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopLevel is Port ( MasterReset : in STD_LOGIC;
Clock : in STD_LOGIC;
CarEW : in STD_LOGIC;
CarNS : in STD_LOGIC;
PedEW : in STD_LOGIC;
PedNS : in STD_LOGIC;
debugLED : out STD_LOGIC;
Lights : out STD_LOGIC_VECTOR (3 downto 0));
end TopLevel;
architecture Behavioral of TopLevel is
-- Synchronized Button inputs --
signal PedEWButton : STD_LOGIC;
signal PedNSButton : STD_LOGIC;
signal CarEWButton : STD_LOGIC;
signal CarNSButton : STD_LOGIC;
--Reset, Clear and Count Signals --
signal ClearRegister : STD_LOGIC;
signal ResetCounter : STD_LOGIC;
signal Count: STD_LOGIC_VECTOR (8 downto 0);
-- Registered Ped Signals --
signal PedEWReg : STD_LOGIC;
signal PedNSReg : STD_LOGIC;
begin
-- Check For MasterReset and Sync Inputs
process (MasterReset, clock, CarEWButton, CarNSButton, PedEWButton, PedNSButton)
begin
if (MasterReset = '1') then
debugLED <= '1';
CarNSButton <= '1';
CarEWButton <= '1';
PedEWButton <= '1';
PedNSButton <= '1';
elsif rising_edge(clock) then
CarEWButton <= CarEW;
CarNSButton <= CarNS;
PedEWButton <= PedEW;
PedNSButton <= PedNS;
end if;
end process;
-- Instantiate State Machine --
StateMachine:
entity work.TrafficStatesMachine
Port Map (
MasterReset => MasterReset,
Clock => Clock,
CarEWButton => CarEWButton,
CarNSButton => CarNSButton,
PedEWButton => PedEWReg,
PedNSButton => PedNSReg,
Counter => Count,
Lights => Lights,
ResetCounter => ResetCounter,
ClearRegister => ClearRegister
);
-- Instantiate Counter --
Counter:
entity work.Counter
Port Map (
MasterReset => MasterReset,
ResetCounter => ResetCounter,
Clock => Clock,
Counter => Count
);
-- Instantiate PedRegister --
PedRegister:
entity work.PedRegister
Port Map (
PedNSButton => PedNSButton,
PedEWButton => PedEWButton,
PedNSRegOut => PedNSReg,
PedEWRegOut => PedEWReg,
ClearRegister => ClearRegister
);
end architecture Behavioral;
--===================================================================
-- Traffic states Machine
--
-- A states Machine to interpret and manage traffic
--
--===================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TrafficStatesMachine is
Port (
MasterReset : IN std_logic;
Clock : IN std_logic;
CarEWButton : IN std_logic;
CarNSButton : IN std_logic;
PedEWButton : IN std_logic;
PedNSButton : IN std_logic;
Counter : IN std_logic_vector(8 downto 0);
ResetCounter : OUT std_logic;
ClearRegister : OUT std_logic;
Lights : OUT std_logic_vector(3 downto 0)
);
end TrafficStatesMachine;
architecture Behavioural of TrafficStatesMachine is
type states_type is (EWCarGreen, EWPedGreen, EWAmber, NSCarGreen, NSPedGreen, NSAmber );
signal states: states_type;
begin
process( MasterReset, Clock, CarEWButton, CarNSButton, PedEWButton, PedNSButton, Counter )
begin
if (MasterReset = '1') then
states <= EWCarGreen;
elsif rising_edge(clock) then
case states is
when EWCarGreen =>
ClearRegister <= '0';
if (Counter < "111111111") then
if (PedEWButton = '1') then
if (CarNSButton = '0') and (PedNSButton = '0') then
states <= EWPedGreen;
ResetCounter <= '1';
else
states <= EWCarGreen;
end if;
end if;
elsif (Counter = "111111111") then
if (CarNSButton = '1') then
states <= EWAmber;
ResetCounter <= '1';
elsif (PedNSButton = '1') then
states <= EWAmber;
ResetCounter <= '1';
else
states <= EWCarGreen;
end if;
end if;
when EWPedGreen =>
ClearRegister <= '1';
ResetCounter <= '0';
if (Counter = "110010000") then
states <= EWCarGreen;
else
states <= EWPedGreen;
end if;
when EWAmber =>
ResetCounter <= '0';
if (Counter = "011001000") then
if (PedNSButton = '1') then
states <= NSPedGreen;
ResetCounter <= '1';
else
states <= NSCarGreen;
ResetCounter <= '1';
end if;
else
states <= EWAmber;
end if;
when NSCarGreen =>
ResetCounter <= '0';
ClearRegister <= '0';
if (Counter < "111111111") then
if (PedNSButton = '1') then
if (CarEWButton = '0') and (PedEWButton = '0') then
states <= NSPedGreen;
ResetCounter <= '1';
else
states <= NSCarGreen;
end if;
end if;
elsif (Counter = "111111111") then
if (CarEWButton = '1') then
states <= NSAmber;
ResetCounter <= '1';
elsif (PedEWButton = '1') then
states <= NSAmber;
ResetCounter <= '1';
else
states <= NSCarGreen;
end if;
end if;
when NSPedGreen =>
ResetCounter <= '0';
ClearRegister <= '1';
if (Counter = "110010000") then
states <= NSCarGreen;
else
states <= NSPedGreen;
end if;
when NSAmber =>
ResetCounter <= '0';
if (Counter = "011001000") then
if (PedEWButton = '1') then
states <= EWPedGreen;
ResetCounter <= '1';
else
states <= EWCarGreen;
ResetCounter <= '1';
end if;
else
states <= NSAmber;
end if;
end case;
end if;
end process;
process( states )
begin
case states is
when EWCarGreen => lights <= "0010";
when EWPedGreen => lights <= "0011";
when EWAmber => lights <= "0001";
when NSCarGreen => lights <= "1000";
when NSPedGreen => lights <= "1100";
when NSAmber => lights <= "0100";
when others => lights <= "0010";
end case;
end process;
end Behavioural;
--===================================================================
-- Counter.vhdl
-- A counter to give time delays
--===================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port ( MasterReset : in std_logic;
Clock : in std_logic;
ResetCounter : in std_logic;
Counter : out std_logic_vector(8 downto 0));
end entity Counter;
architecture Behavioural of Counter is
signal Count : std_logic_vector(8 downto 0);
begin
Counter <= Count;
-- Produce Count sequence from 0 ... 512
process( MasterReset, Clock, ResetCounter)
begin
if (MasterReset = '1') then
Count <= "000000000"; -- start count from 0
elsif rising_edge(clock) then
if (ResetCounter = '1') then
Count <= "000000000";
elsif (Count < "111111111") then
Count <= Count + "000000001";
else
Count <= "111111111";
end if;
end if;
end process;
end architecture Behavioural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PedRegister is
Port ( ClearRegister : in STD_LOGIC;
PedNSButton: in STD_LOGIC;
PedEWButton : in STD_LOGIC;
PedNSRegOut : out STD_LOGIC;
PedEWRegOut : out STD_LOGIC);
end PedRegister;
architecture Behavioral of PedRegister is
signal PedNSReg : STD_LOGIC;
signal PedEWReg : STD_LOGIC;
begin
PedNSRegOut <= PedNSReg;
PedEWRegOut <= PedEWReg;
process (PedNSButton, PedEWButton, ClearRegister)
begin
if ClearRegister = '1' then
PedNSReg <='0';
elsif PedNSButton = '1' then
PedNSReg <='1';
else
PedNSReg <= '0';
end if;
if ClearRegister = '1' then
PedEWReg <= '0';
elsif PedEWButton = '1' then
PedEWReg <='1';
else
PedEWReg <= '0';
end if;
end process;
end Behavioral;
--===================================================================
--交通状态机
--
--用于解释和管理流量的状态机
--
--===================================================================
图书馆IEEE；
使用IEEE.STD_LOGIC_1164.ALL；
使用IEEE.STD_LOGIC_ARITH.ALL；
使用IEEE.STD_LOGIC_UNSIGNED.ALL；
实体流量状态为
港口(
主复位：在标准逻辑中；
时钟：标准逻辑；
CarEWButton：在标准逻辑中；
卡恩斯顿：标准逻辑；
PEDEWBUTON：在标准逻辑中；
PedNSButton：标准逻辑中；
计数器：标准逻辑向量（8到0）；
复位计数器：输出标准_逻辑；
清除寄存器：输出标准逻辑；
灯：输出标准逻辑向量（3到0）
);
终端流量；
交通状态的建筑行为
类型状态\u类型为（EWCarGreen、EWPedGreen、eMember、NSCarGreen、NSPedGreen、NSAmber）；
信号状态：状态\ U型；
开始
过程（主复位、时钟、CarEWButton、CarNSButton、PedwButton、PedNSButton、计数器）
开始
如果（主复位='1'），则
州
ClearRegister描述了类似的情况
在本例中，Xilinx ISE版本存在问题。我复制了你的代码，并用ISE 13.4进行了检查，计数器已连接
但是，与您的功能相关的是“真实”合成（检查合成报告），而不是RTL示意图可视化。类似的情况也有描述
在本例中，Xilinx ISE版本存在问题。我复制了你的代码，并用ISE 13.4进行了检查，计数器已连接
但是，与您的功能相关的是“真实”合成（检查合成报告）而不是RTL原理图可视化。显而易见的问题更相关，因为您没有包括测试台：它在模拟中工作吗？显而易见的问题更相关，因为您没有包括测试台：它在模拟中工作吗？