16位VHDL微处理器
我正在尝试做一个微处理器架构,但我被卡住了。我的蓄能器、红外和个人电脑似乎不工作,我不知道为什么。 它们的输出总是不确定的。我检查了映射和mp的其他组件,它们都是正确的。问题出在这些寄存器的某个地方16位VHDL微处理器,vhdl,Vhdl,我正在尝试做一个微处理器架构,但我被卡住了。我的蓄能器、红外和个人电脑似乎不工作,我不知道为什么。 它们的输出总是不确定的。我检查了映射和mp的其他组件,它们都是正确的。问题出在这些寄存器的某个地方 ------------------------------------------------------ -- ALU ------------------------------------------------------ library IEEE; use IEEE
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-- ALU
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.up_pack.all;
entity alu is
port ( A, B : in std_logic_vector(15 downto 0);
alufs : in ALU_FCTS;
S : out std_logic_vector( 15 downto 0));
end alu;
architecture arch_alu of alu is
begin
S <= "0000000000000000"; -- sortie par défaut
process(A, B, alufs)
begin
case alufs is
when ALU_B => S <= B;
when ALU_SUB => S <= std_logic_vector(unsigned(B) - unsigned(A));
when ALU_ADD => S <= std_logic_vector(unsigned(B) + unsigned(A));
when ALU_B_INC => S <= std_logic_vector(unsigned(B) + 1);
when ALU_AND => S <= A and B;
when ALU_OR => S <= A or B;
when ALU_XOR => S <= A xor B;
when others => S <= "0000000000000000";
end case;
end process;
end arch_alu;
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-- ACCUMULATER
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity accumulator is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0);
acc15, accz : out std_logic );
end accumulator;
architecture arch_acc of accumulator is
signal q_reg : std_logic_vector(15 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then q_reg <= (others => '0');
elsif load='1' then q_reg <= std_logic_vector(unsigned(q_reg) + unsigned(data_in)); end if;
end if;
end process;
data_out <= q_reg;
acc15 <= q_reg(15);
accz <= '1' when q_reg = "0000000000000000";
end arch_acc;
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-- REGISTER PC
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pc_reg is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(11 downto 0) );
end pc_reg;
architecture arch_pc_reg of pc_reg is
signal interne : std_logic_vector(11 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then interne <= (others => '0');
elsif load='1' then interne <= data_in;
end if;
end if;
end process;
data_out <= interne;
end arch_pc_reg;
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-- IR (Instruction Register)
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.up_pack.all;
entity ir_reg is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(11 downto 0);
opcode : out OPCODE);
end ir_reg;
architecture arch_ir_reg of ir_reg is
signal interne : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then data_out <= (others => '0');
elsif load='1'
then
data_out <= data_in(11 downto 0);
interne <= data_in(15 downto 12);
end if;
end if;
end process;
opcode <= OP_LDA when interne="0000" else
OP_STO when interne="0001" else
OP_ADD when interne="0010" else
OP_SUB when interne="0011" else
OP_JMP when interne="0100" else
OP_JGE when interne="0101" else
OP_JNE when interne="0110" else
OP_STP when interne="0111" else
OP_AND when interne="1000" else
OP_OR when interne="1001" else
OP_XOR when interne="1010" else
OP_LDR when interne="1011" else
OP_LDI when interne="1100" else
OP_STI when interne="1101" else
OP_JSR when interne="1110" else
OP_RET when interne="1111" else
OP_UNKNOWN;
end arch_ir_reg;
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--阿卢
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图书馆IEEE;
使用IEEE.std_logic_1164.all;
使用IEEE.numeric_std.all;
使用work.up_pack.all;
实体alu是
端口(A,B:标准逻辑向量(15到0);
alufs:在ALU_FCTS中;
S:输出标准逻辑向量(15到0);
末端alu;
alu的建筑arch_alu是
开始
这不是答案,而是供您使用的测试台。你的蓄能器似乎工作正常。我用下面的测试台测试了它。将其用作为其余模块编写测试台的资源。(您可以编写一个测试台,一起或单独测试所有模块,仅供参考)
IEEE库;
使用IEEE.std_logic_1164.all;
使用IEEE.numeric_std.all;
实体tb_累加器为
末端tb_蓄能器;
tb_累加器的体系结构行为是
信号时钟:标准逻辑:='0';
信号raz:std_逻辑:='1';
信号负载:标准逻辑:='0';
信号数据输入:标准逻辑向量(15到0):=(其他=>'0');
信号数据输出:标准逻辑向量(15到0):=(其他=>'0');
信号acc15:std_逻辑:='0';
信号accz:std_逻辑:='0';
开始
--为传入累加器的信号赋值。
时钟数据输入,
数据输出=>数据输出,
acc15=>acc15,
accz=>accz
);
结束行为;
如果没有密码,很难准确说出问题所在。您是否将所有输入连接到测试台中的某个东西?您是否有特定的问题?A将提供错误消息以及再现它们的方法。I使用强制变量进行测试。我知道这不是一个好的练习,但我还是个初学者。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_accumulator is
end tb_accumulator;
architecture behav of tb_accumulator is
signal clk : std_logic := '0';
signal raz : std_logic := '1';
signal load : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal data_out : std_logic_vector(15 downto 0) := (others => '0');
signal acc15 : std_logic := '0';
signal accz : std_logic := '0';
begin
--Assign values for signals being passed into accumulator.
clk <= not clk after 2.5 ns;
data_in <= "0000000000000001";
raz <= '0' after 90 ns; --You can do this instead of forcing a signal. Set at what times you want it to change values.
load <= '1' after 100 ns;
accu_inst : entity work.accumulator
port map(
clk => clk,
raz => raz,
load => load,
data_in => data_in,
data_out => data_out,
acc15 => acc15,
accz=> accz
);
end behav;