Vhdl 为什么我在合成时看不到输出？

我一直在做一项几乎已经完成的实验任务，但遇到了一个问题，在合成时我看不到输出。我有7个模块，单独测试时显示正确的输出。为什么我在使用顶级模块和测试台文件时根本不会得到任何输出？下面是我的顶部模块，后面是我的测试台，因为我怀疑可能存在问题。我已经检查过了，找不出我做错了什么。任何帮助都将不胜感激

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_module is port(
    x,y : in std_logic_vector(7 downto 0);
    opcode : in std_logic_vector(2 downto 0);
    z : out std_logic_vector(7 downto 0)
    );
end top_module;

architecture behavior of top_module is

signal bwAnd, bwOr, bwXor, add, subtract, bwComplement, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6 : std_logic_vector(7 downto 0);


component BW_And is port(
    x,y : in std_logic_vector(7 downto 0);
    z1 : out std_logic_vector(7 downto 0)
    );
end component;

component BW_Rr is port(
    x,y : in std_logic_vector(7 downto 0);
    z2 : out std_logic_vector(7 downto 0)
    );
end component;

component BW_Xor is port(
    x,y : in std_logic_vector(7 downto 0);
    z3 : out std_logic_vector(7 downto 0)
    );
end component;

component full_adder_8 is port(
    x,y : in std_logic_vector(7 downto 0);
    cin : in std_logic_vector(7 downto 0) := "00000000";
    sum, cout: out std_logic_vector(7 downto 0)
    );
end component;

component full_subtractor_8 is port(
    x,y : in std_logic_vector(7 downto 0);
    cin : in std_logic_vector(7 downto 0) := "11111111";
difference, cout: out std_logic_vector(7 downto 0)
    );
end component;

component Complement is port(
    x : in std_logic_vector(7 downto 0);
    z4 : out std_logic_vector(7 downto 0)
    );
end component;

component mux is port(
    z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0);
    opcode : in std_logic_vector(2 downto 0);
    mux_out : out std_logic_vector(7 downto 0)
    );
end component;

begin

--instantiating components and mapping ports

c0: BW_And port map(x => x, y => y, z1 => bwAnd);

c1: BW_Or port map(x => x, y => y, z2 => bwOr);

c2: BW_Xor port map(x => x, y => y, z3 => bwXor);

c3: full_adder_8 port map(x => x, y => y, sum => add);

c4: full_subtractor_8 port map(x => x, y => y, difference => subtract);

c5: Complement port map(x => x, z4 => bwComplement);

c6: mux port map(z1 => mux_in1, z2 => mux_in2, z3 => mux_in3, sum => mux_in4, difference => mux_in5, z4 =>mux_in6, opcode => opcode, mux_out => z);

end behavior;

试验台：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab4 is
end Lab4;

architecture behavior of Lab4 is

component top_module is port(
    x,y : in std_logic_vector(7 downto 0);
    opcode : in std_logic_vector(2 downto 0);
    z : out std_logic_vector(7 downto 0)
    );
end component;

signal test_x : std_logic_vector(7 downto 0);
signal test_y : std_logic_vector(7 downto 0);
signal test_opcode : std_logic_vector(2 downto 0) := "000";
signal test_z : std_logic_vector(7 downto 0);

begin

    uut: top_module port map (x => test_x, y => test_y, opcode => test_opcode, z => test_z);

sim_proc : process
begin

    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "000";
    wait for 100 ns;
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "001";
    wait for 100 ns;
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "010";
    wait for 100 ns;
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "011";
    wait for 100 ns;
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "100";
    wait for 100 ns;
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "101";

end process;
end behavior;

---

我终于意识到我的问题出在哪里了。问题是我的mux文件。在我的过程中，我只传递了操作码，而忽略了传递所有的输入

之前：

process (opcode)
    .
    .
    .
end process;

之后：

process (z1,z2,z3,sum,difference,z4,opcode)
    .
    .
    .
end process;

---

与您的7个组件相对应的实体在哪里？@MatthewTaylor这些实体位于不同的文件中。例如：bw_和.vhd、bw_或.vhd等分别定义。它们包括实体和架构。输出z由mux驱动，但正如Matthew所指出的，该实体不包括在内，因此无法确定输出有什么问题。顺便说一句。请创建一个，因为这样做可能会暴露问题，并使其他人更容易提供帮助。@MortenZilmer我已按要求为所有组件添加了实体。您不会将输入传递给进程。这是一个过程敏感性列表。参见IEEE Std 1076-2008 11.3过程语句，作为过程中最后一条语句的隐式等待语句的灵敏度列表。敏感度列表通常与合成无关。请考虑将问题提出来。

process (z1,z2,z3,sum,difference,z4,opcode)
    .
    .
    .
end process;