Vhdl wait必须包含带有until关键字的条件子句

以下VHDL用于测试booth乘法器。在分析和精化过程中，我在第一个wait语句中不断遇到一个错误：wait语句必须包含带有until关键字的condition子句 我有几个这样编写的工作测试台，即信号分配，等待x ns，其他分配，等待x ns。。。。我似乎找不到可能的错误

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

---

代码中唯一可观察到的错误是：

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

应该是：

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

在实体和体系结构对之前使用虚拟BoothMultiplier32并使用上述校正：

library ieee;
use ieee.std_logic_1164.all;

entity boothmultiplier_32 is
    port (
        dataa, datab    :   in std_logic_vector (31 downto 0);
        result          :   out std_logic_vector (63 downto 0)
    );
end entity;

architecture foo of boothmultiplier_32 is
begin
end architecture;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

然后，代码使用精化和运行目标boothMultiplier_32_测试进行分析、精化和运行，虽然没有做任何有趣的事情，但仍然显示出正确的连接

也许你能告诉我们你用的是什么工具