Vhdl 如何将一个模块的输出信号连接到另一个模块的输入信号
假设我的VHDL代码如下所示:Vhdl 如何将一个模块的输出信号连接到另一个模块的输入信号,vhdl,Vhdl,假设我的VHDL代码如下所示: entity x1: port(a: out std_logic; .... .... ); architecture behv1 of x1 is .... end behv1; entity y1 port(b: in std_logic; .... .... ); architecture behv1 of y1 is begin m1: x1 port map(a=>b); end behv1; entity x1: port(a: o
entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
....
end behv1;
entity y1
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
m1: x1 port map(a=>b);
end behv1;
entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
-- Do something...
end behv1;
entity y1
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
-- Do something...
end behv1;
entity toplevel
port (
clk : in std_logic;
...
);
architecture toplevel_arch of toplevel is
signal x1_output : std_logic; -- Temp to connect both modules
begin
m_x1: x1 port map(a => x1_output);
m_y1: y1 port map(b => x1_output);
end toplevel_arch;
因此,这里a是实体x1的输出信号,它直接连接到其他实体y1的输入b您的操作方式有点错误
实体y1
提供了y1
实体的接口。它指定您有实体的输入,b
。这意味着您可以从architecture
声明中读取b
的值。然后,您应该实现您的y1
模块在architecture behav1
中要做的事情
根据我的理解,您需要实例化x1
和y1
,然后将它们连接在一起。要做到这一点,您需要提供x1
和y1
的实现,然后在一个单独的顶层中实例化这两者并将它们连接在一起。大概是这样的:
entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
....
end behv1;
entity y1
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
m1: x1 port map(a=>b);
end behv1;
entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
-- Do something...
end behv1;
entity y1
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
-- Do something...
end behv1;
entity toplevel
port (
clk : in std_logic;
...
);
architecture toplevel_arch of toplevel is
signal x1_output : std_logic; -- Temp to connect both modules
begin
m_x1: x1 port map(a => x1_output);
m_y1: y1 port map(b => x1_output);
end toplevel_arch;
下面的示例分析、阐述和模拟 它说明了如何按层次连接输入和输出
library ieee;
use ieee.std_logic_1164.all;
entity x3 is
port (
x3in: in std_logic;
x3out: out std_logic
);
end entity;
architecture behv3 of x3 is
begin
x3out <= x3in;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity y3 is
port (
y3in: in std_logic;
y3out: out std_logic
);
end entity;
architecture behv3 of y3 is
begin
y3out <= y3in;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity z3 is
port (
z3in: in std_logic;
z3out: out std_logic
);
end entity;
architecture foo of z3 is
component x3 is
port (
x3in: in std_logic;
x3out: out std_logic
);
end component;
component y3 is
port (
y3in: in std_logic;
y3out: out std_logic
);
end component;
signal x3out: std_logic;
begin
u0:
x3
port map (
x3in => z3in,
x3out => x3out
);
u1:
y3
port map (
y3in => x3out,
y3out => z3out
);
end architecture;
ieee库;
使用ieee.std_logic_1164.all;
实体x3是
港口(
x3in:in标准逻辑;
x3out:out标准逻辑
);
终端实体;
x3的体系结构是
开始
x3out x3out
);
u1:
y3
港口地图(
y3in=>x3out,
y3out=>z3out
);
终端架构;
可在语言参考手册(LRM)、IEEE Std 1076-2008 6.5.6.3端口条款中找到适用规则:
在完整阐述了给定的描述(见第14条)后,如果正式端口与实际端口相关联,则根据正式端口的模式(见6.5.2)(如有),适用以下限制:
a) 对于正式的模式输入端口,相关的实际端口应为模式输入、输出、输入或缓冲端口。此限制既适用于在关联元素的实际部分中作为名称关联的实际值,也适用于在关联元素的实际部分中作为表达式的一部分关联的实际值。b) 对于正式的模式输出端口,相关的实际端口应为模式输出端口、输入输出端口或缓冲区。
c) 对于模式输入输出的正式端口,相关的实际端口应为模式输出端口、输入输出端口或缓冲区。
d) 对于正式的模式缓冲端口,相关的实际端口应为模式输出端口、输入端口或缓冲端口。
e) 对于模式链接的正式端口,关联的实际端口可以是任何模式的端口
thanx,它真的帮助了我。