VHDL中寄存器的多次读取和封装导致错误值
我目前面临一个问题,读取两个寄存器并通过代理将其值发送到FPGA上的磁贴。编码信号有三个输入通道,由频率为50khz的脉冲组成,然后通过FPGA板上的本地100Mhz时钟对信号进行采样。在模块中,对两个通道的脉冲进行计数,我使用位移位进行封装,将两个计数器的读取值放入一个32位std_位_向量中,通过代理发送 若我只传输一个通道的计数值,并通过代理信号发送它们,那个么它的行为总是正确的。然而,当从两个寄存器读取两个计数值并进行封装时,移位值的16个高位总是以比预期更快的速度增加。换言之,计数过程ifself是正确的,同时计数模块和磁贴之间的通信也没有问题 我不知道这个问题是由于进程从两个寄存器读取太快而导致同步问题造成的。一个通道输入信号每500个计数只增加一个,而另一个每旋转500个。一个旋转由编码器上的手控制(然后你可以想象输入信号的低频率) 然后在模块的最后两行进行封装。 提前谢谢 计数模块设计如下:VHDL中寄存器的多次读取和封装导致错误值,vhdl,encapsulation,multiple-records,Vhdl,Encapsulation,Multiple Records,我目前面临一个问题,读取两个寄存器并通过代理将其值发送到FPGA上的磁贴。编码信号有三个输入通道,由频率为50khz的脉冲组成,然后通过FPGA板上的本地100Mhz时钟对信号进行采样。在模块中,对两个通道的脉冲进行计数,我使用位移位进行封装,将两个计数器的读取值放入一个32位std_位_向量中,通过代理发送 若我只传输一个通道的计数值,并通过代理信号发送它们,那个么它的行为总是正确的。然而,当从两个寄存器读取两个计数值并进行封装时,移位值的16个高位总是以比预期更快的速度增加。换言之,计数过程
library rdt_dtl_proxy_targetlib;
use rdt_dtl_proxy_targetlib.rdt_dtl_proxy_target_cmp_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_ARITH.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity dtl_pmod_rotary is
generic (
WIDTH_DTL_CMD_ADDR : natural:= 32;
WIDTH_DTL_CMD_BLOCK_SIZE : natural:= 5;
WIDTH_DTL_DATA : natural:= 32;
WIDTH_DTL_WR_MASK : natural:= 4
);
port (
clk : in std_logic;
rst_n : in std_logic;
rotary_a : in std_logic;
rotary_b : in std_logic;
rotary_i : in std_logic;
dtl_cmd_valid_t_proxy0 : in std_logic;
dtl_cmd_accept_t_proxy0 : out std_logic;
dtl_cmd_addr_t_proxy0 : in std_logic_vector(WIDTH_DTL_CMD_ADDR - 1 downto 0);
dtl_cmd_read_t_proxy0 : in std_logic;
dtl_cmd_block_size_t_proxy0 : in std_logic_vector(WIDTH_DTL_CMD_BLOCK_SIZE - 1 downto 0);
dtl_wr_valid_t_proxy0 : in std_logic;
dtl_wr_last_t_proxy0 : in std_logic;
dtl_wr_accept_t_proxy0 : out std_logic;
dtl_wr_data_t_proxy0 : in std_logic_vector(WIDTH_DTL_DATA - 1 downto 0);
dtl_wr_mask_t_proxy0 : in std_logic_vector(WIDTH_DTL_WR_MASK - 1 downto 0);
dtl_rd_last_t_proxy0 : out std_logic;
dtl_rd_valid_t_proxy0 : out std_logic;
dtl_rd_accept_t_proxy0 : in std_logic;
dtl_rd_data_t_proxy0 : out std_logic_vector(WIDTH_DTL_DATA - 1 downto 0)
);
end dtl_pmod_rotary;
architecture rtl of dtl_pmod_rotary is
signal dtl_rd_data_15 : std_logic_vector(WIDTH_DTL_DATA - 1 downto 0);
signal dtl_rd_accept_14 : std_logic;
signal dtl_cmd_block_size_6 : std_logic_vector(WIDTH_DTL_CMD_BLOCK_SIZE - 1 downto 0);
signal dtl_wr_data_10 : std_logic_vector(WIDTH_DTL_DATA - 1 downto 0);
signal dtl_cmd_read_5 : std_logic;
signal dtl_rd_last_12 : std_logic;
signal dtl_rst_n_1 : std_logic;
signal dtl_wr_valid_7 : std_logic;
signal dtl_wr_accept_9 : std_logic;
signal dtl_wr_last_8 : std_logic;
signal dtl_cmd_addr_4 : std_logic_vector(WIDTH_DTL_CMD_ADDR - 1 downto 0);
signal dtl_cmd_valid_2 : std_logic;
signal dtl_clk_0 : std_logic;
signal dtl_rd_valid_13 : std_logic;
signal dtl_wr_mask_11 : std_logic_vector(WIDTH_DTL_WR_MASK - 1 downto 0);
signal dtl_cmd_accept_3 : std_logic;
-- signals for counting
signal cnt_r : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal cnt_r_a : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal cnt_r_b : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal cnt_r_i : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal cnt_nxt_a : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal cnt_nxt_b : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal cnt_nxt_i : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal cnt_ref_i : std_logic_vector(WIDTH_DTL_DATA-1 downto 0) := X"00000000";
signal rotary_a_r : std_logic; --register storing data from rotary_a.
signal rotary_a_2r : std_logic; --register storing data from rotary_a_r
signal rotary_b_r : std_logic; --register storing data from rotary_b.
signal rotary_b_2r : std_logic; --register storing data from rotary_b_r
signal rotary_i_r : std_logic; --register storing data from rotary_i.
signal rotary_i_2r : std_logic; --register storing data from rotary_i_r
begin
dtl_clk_0 <= clk;
dtl_rst_n_1 <= rst_n;
dtl_cmd_valid_2 <= dtl_cmd_valid_t_proxy0;
dtl_cmd_accept_t_proxy0 <= dtl_cmd_accept_3;
dtl_cmd_addr_4 <= dtl_cmd_addr_t_proxy0;
dtl_cmd_read_5 <= dtl_cmd_read_t_proxy0;
dtl_cmd_block_size_6 <= dtl_cmd_block_size_t_proxy0;
dtl_wr_valid_7 <= dtl_wr_valid_t_proxy0;
dtl_wr_last_8 <= dtl_wr_last_t_proxy0;
dtl_wr_accept_t_proxy0 <= dtl_wr_accept_9;
dtl_wr_data_10 <= dtl_wr_data_t_proxy0;
dtl_wr_mask_11 <= dtl_wr_mask_t_proxy0;
dtl_rd_last_t_proxy0 <= dtl_rd_last_12;
dtl_rd_valid_t_proxy0 <= dtl_rd_valid_13;
dtl_rd_accept_14 <= dtl_rd_accept_t_proxy0;
dtl_rd_data_t_proxy0 <= dtl_rd_data_15;
-- Begin child instances
proxy0 : rdt_dtl_proxy_target
generic map (
DTL_DATA_WIDTH => WIDTH_DTL_DATA,
DTL_ADDR_WIDTH => WIDTH_DTL_CMD_ADDR,
DTL_BLK_SIZE_WIDTH => WIDTH_DTL_CMD_BLOCK_SIZE,
DTL_WR_MASK_WIDTH => WIDTH_DTL_WR_MASK
)
port map (
dtl_clk => dtl_clk_0,
dtl_rst_n => dtl_rst_n_1,
dtl_cmd_accept_t => dtl_cmd_accept_3,
dtl_cmd_addr_t => dtl_cmd_addr_4,
dtl_cmd_block_size_t => dtl_cmd_block_size_6,
dtl_cmd_read_t => dtl_cmd_read_5,
dtl_cmd_valid_t => dtl_cmd_valid_2,
dtl_rd_accept_t => dtl_rd_accept_14,
dtl_rd_data_t => dtl_rd_data_15,
dtl_rd_last_t => dtl_rd_last_12,
dtl_rd_valid_t => dtl_rd_valid_13,
dtl_wr_accept_t => dtl_wr_accept_9,
dtl_wr_data_t => dtl_wr_data_10,
dtl_wr_last_t => dtl_wr_last_8,
dtl_wr_mask_t => dtl_wr_mask_11,
dtl_wr_valid_t => dtl_wr_valid_7,
cmd_accept => '1', --target accept handshake,input port of Proxy
cmd_addr => open,
cmd_block_size => open,
cmd_read => open, --output port of Proxy
cmd_valid => open, --output port of Proxy
rd_accept => open, --output port of Proxy, return the accept info from initializer
--rd_data => x"00000003", --test value
rd_data => cnt_r, --input port of proxy, for sending the counter value
rd_last => '1',
rd_valid => '1',
wr_accept => '0', --return value to Proxy indicating prepared for receiving written data from initiator
wr_data => open, --receive data from Proxy that written by initializer
wr_last => open,
wr_mask => open,
wr_valid => open
);
-- Counting pulses
-- combinatorial process
comb_counter_process_a : process(rotary_a_r, rotary_a_2r)
begin
if rotary_a_r = '1' and rotary_a_2r = '0' then
cnt_nxt_a <= cnt_r_a + 1;
else
cnt_nxt_a <= cnt_r_a;
end if;
end process;
-- sequential process with synchronous reset
seq_counter_process_a : process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
cnt_r_a <= (others => '0');
rotary_a_r <= '0';
rotary_a_2r <= '0';
else
-- registering
cnt_r_a <= cnt_nxt_a ;
rotary_a_2r <= rotary_a_r;
rotary_a_r <= rotary_a;
--cnt_r <= cnt_r_a(8 downto 0);
end if;
end if;
end process;
comb_counter_process_b : process(rotary_b_r, rotary_b_2r)
begin
if rotary_b_r = '1' and rotary_b_2r = '0' then
cnt_nxt_b <= cnt_r_b + 1;
else
cnt_nxt_b <= cnt_r_b;
end if;
end process;
-- sequential process with synchronous reset
seq_counter_process_b : process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
cnt_r_b <= (others => '0');
rotary_b_r <= '0';
rotary_b_2r <= '0';
else
-- registering
cnt_r_b <= cnt_nxt_b;
rotary_b_2r <= rotary_b_r;
rotary_b_r <= rotary_b;
--cnt_r(31 downto 16) <= X"ABCD";
end if;
end if;
end process;
comb_counter_process_i : process(rotary_i_r, rotary_i_2r)
begin
if rotary_i_r = '1' and rotary_i_2r = '0' then
cnt_nxt_i <= cnt_r_i + 1;
else
cnt_nxt_i <= cnt_r_i;
end if;
end process;
-- sequential process with synchronous reset
seq_counter_process_i : process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
cnt_r_i <= (others => '0');
rotary_i_r <= '0';
rotary_i_2r <= '0';
else
-- registering
cnt_r_i <= cnt_nxt_i;
rotary_i_2r <= rotary_i_r;
rotary_i_r <= rotary_i;
--cnt_r(15 downto 0) <= X"1234"; --the digits for cnt_r_i may change
end if;
end if;
end process;
cnt_r(31 downto 16) <= cnt_r_b(15 downto 0);
cnt_r(15 downto 0) <= cnt_r_i(15 downto 0);
end rtl;
库rdt\u dtl\u proxy\u targetlib;
使用rdt_dtl_proxy_targetlib.rdt_dtl_proxy_target_cmp_pkg.all;
图书馆ieee;
使用ieee.std_logic_1164.all;
使用ieee.std_logic_ARITH.all;
使用ieee.std_logic_unsigned.all;
使用ieee.numeric_std.all;
实体dtl_pmod_旋转是
一般的(
宽度\u DTL\u CMD\u地址:自然:=32;
宽度\u DTL\u CMD\u块大小:自然=5;
宽度DTL_数据:自然=32;
宽度\u DTL\u WR\u遮罩:自然=4
);
港口(
clk:标准逻辑中;
rst_n:标准逻辑中;
旋转a:标准逻辑;
旋转b:标准逻辑;
旋转i:标准逻辑;
dtl_cmd_valid_t_proxy0:标准逻辑中;
dtl_cmd_accept_t_proxy0:输出标准逻辑;
dtl_cmd_addr_t_proxy0:在标准逻辑向量中(宽度\u dtl_cmd_addr-1向下至0);
dtl_cmd_read_t_proxy0:标准逻辑中;
dtl\U cmd\U block\U size\U t\U proxy0:在标准逻辑向量中(宽度\U dtl\U cmd\U block\U size-1向下至0);
dtl_wr_valid_t_proxy0:标准逻辑中;
dtl_wr_last_t_proxy0:标准逻辑中;
dtl_wr_accept_t_proxy0:输出标准逻辑;
dtl\u wr\u data\u t\u proxy0:在标准逻辑向量中(宽度\u dtl\u data-1到0);
dtl_wr_mask_t_proxy0:在标准逻辑向量中(宽度\u dtl_wr_mask-1到0);
dtl_rd_last_t_proxy0:输出标准逻辑;
dtl_rd_valid_t_proxy0:输出标准逻辑;
dtl_rd_accept_t_proxy0:标准逻辑中;
dtl\U rd\U数据代理0:out标准逻辑向量(宽度\U dtl\U数据-1到0)
);
结束dtl_pmod_旋转;
dtl_pmod_rotary的体系结构rtl是
信号dtl\U rd\U数据\U 15:标准逻辑向量(宽度\U dtl\U数据-1向下至0);
信号dtl_rd_accept_14:标准逻辑;
信号dtl\U cmd\U block\U size\U 6:std\U逻辑\U矢量(宽度\U dtl\U cmd\U block\U size-1向下至0);
信号dtl_wr_数据_10:std_逻辑_矢量(宽度\u dtl_数据-1向下至0);
信号dtl_cmd_read_5:标准逻辑;
信号dtl_rd_last_12:标准逻辑;
信号dtl_rst_n_1:标准逻辑;
信号dtl_wr_有效_7:标准逻辑;
信号dtl_wr_accept_9:标准逻辑;
信号dtl_wr_last_8:标准逻辑;
信号dtl_cmd_addr_4:std_逻辑_向量(宽度\u dtl_cmd_addr-1向下至0);
信号dtl_cmd_valid_2:标准逻辑;
信号dtl_clk_0:标准逻辑;
信号dtl_rd_有效_13:标准逻辑;
信号dtl_wr_屏蔽11:std_逻辑_矢量(宽度\u dtl_wr_屏蔽-1向下至0);
信号dtl_cmd_accept_3:标准逻辑;
--计数信号
信号cnt\u r:std\u逻辑向量(宽度\u DTL\u数据-1向下至0):=X“00000000”;
信号cnt_r_a:std_逻辑_向量(宽度\u DTL_数据-1向下至0):=X“00000000”;
信号cnt_r_b:std_逻辑_向量(宽度_DTL_数据-1向下至0):=X“00000000”;
信号cnt_r_i:std_逻辑_向量(宽度_DTL_数据-1向下至0):=X“00000000”;
信号cnt_nxt_a:std_逻辑_矢量(宽度_DTL_数据-1向下至0):=X“00000000”;
信号cnt_nxt_b:std_逻辑_向量(宽度_DTL_数据-1向下至0):=X“00000000”;
信号cnt\u nxt\u i:std\u逻辑向量(宽度\u DTL\u数据-1向下至0):=X“00000000”;
信号cnt_ref_i:std_逻辑_向量(宽度\u DTL_数据-1向下至0):=X“00000000”;
信号旋转:标准逻辑--存储来自rotary_a的数据的寄存器。
信号旋转2r:标准逻辑--存储来自rotary\u a\r的数据的寄存器
信号旋转:标准逻辑--存储来自rotary_b的数据的寄存器。
信号旋转_b_2r:标准_逻辑--存储来自rotary_b_r的数据的寄存器
信号旋转:标准逻辑--存储来自rotary_i的数据的寄存器。
信号旋转接口2r:标准逻辑--存储来自rotary_i_r的数据的寄存器
开始
dtl_clk_0 dtl_wr_accept_9,
dtl_wr_data_t=>dtl_wr_data_10,
dtl_wr_last_t=>dtl_wr_last_8,
dtl_wr_mask_t=>dtl_wr_mask_11,
dtl_wr_valid_t=>dtl_wr_valid_7,
cmd_accept=>'1',--目标接受握手,代理的输入端口
cmd_addr=>打开,
cmd_block_size=>打开,
cmd_read=>open,--代理的输出端口
cmd_valid=>open,--代理的输出端口
rd_accept=>open,--代理的输出端口,从初始值设定项返回接受信息
--rd_数据=>x“00000003”,--测试值
rd_data=>cnt_r,--代理的输入端口,用于发送计数器值
rd_last=>“1”,
rd_valid=>“1”,
wr_accept=>'0',--向代理返回值,指示已准备好从启动器接收书面数据
wr_data=>open,--从初始值设定项写入的代理接收数据
wr_last=>打开,