Embedded MSP430-XT1晶体在LPM3中关闭
我使用的是MSP430F6638控制器。 根据数据表ACLK,在LPM3(深度睡眠)中,不会关闭源时钟(ACLK源自源时钟) 但在我的例子中,只要我进入LPM3,XT1就会停止振荡 上述情况仅在XT2晶体关闭时发生。如果XT2未关闭,然后进入LPM3,则XT1保持振荡 我如何配置时钟Embedded MSP430-XT1晶体在LPM3中关闭,embedded,msp430,iar,Embedded,Msp430,Iar,我使用的是MSP430F6638控制器。 根据数据表ACLK,在LPM3(深度睡眠)中,不会关闭源时钟(ACLK源自源时钟) 但在我的例子中,只要我进入LPM3,XT1就会停止振荡 上述情况仅在XT2晶体关闭时发生。如果XT2未关闭,然后进入LPM3,则XT1保持振荡 我如何配置时钟 P3SEL |= BIT4; // SMCLK P3DIR |= BIT4; P7SEL |= 0x0C; // P7.3,2 -> XT2OUT, XT2IN // Unlock
P3SEL |= BIT4; // SMCLK
P3DIR |= BIT4;
P7SEL |= 0x0C; // P7.3,2 -> XT2OUT, XT2IN
// Unlock XT1 pins for operation
while(BAKCTL & LOCKBAK)
{
BAKCTL &= ~(LOCKBAK);
}
// From XT2 = 16 Mhz
UCSCTL6 |= XCAP_2; // Fz 120216: Internal load cap (CAP Value + 2)/2 = 8.5pF (Refer Datasheet)
UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0 | XT2DRIVE1);
UCSCTL6 |= (XT2DRIVE0);
UCSCTL6 &= ~XT2OFF; // Set XT2 On
UCSCTL6 &= ~XT1OFF; // Set XT1 On
UCSCTL3 = 0x0021; // FLL : REFOCLK and divby2
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG); // Clear XT1 fault flags
}while(UCSCTL7 & (XT2OFFG + XT1LFOFFG)); // Test XT1 fault flag
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x1F00; //Range
UCSCTL1 = 0x50; //Range
UCSCTL2 = 0x1138; // MCLK : 5 Mhz
_delay_ms(100);
// Clock Source Selection :
UCSCTL4 = 0x0054; // ACLK : XT1CLK; SMCLK : XT2CLK; MCLK : DCOCLKDIV
UCSCTL5 |= DIVS1; // SMCLK div by 4 (4 Mhz)
UCSCTL3 |= 0x0021; // FLLRef : REF0; FLLRef/2 => MCLK = 5Mhz
// Enable the FLL control loop
__bic_SR_register(SCG0);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); // Clear XT2,XT1,DCO fault flags; XT1HFOFFG
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while(SFRIFG1 & OFIFG); // Test oscillator fault flag
我是如何从XT2退出的:
UCSCTL6 |= (SMCLKOFF);
_delay_ms(10);
UCSCTL6 |= (XT2OFF);
晶体源
P3SEL |= BIT4; // SMCLK
P3DIR |= BIT4;
P7SEL |= 0x0C; // P7.3,2 -> XT2OUT, XT2IN
// Unlock XT1 pins for operation
while(BAKCTL & LOCKBAK)
{
BAKCTL &= ~(LOCKBAK);
}
// From XT2 = 16 Mhz
UCSCTL6 |= XCAP_2; // Fz 120216: Internal load cap (CAP Value + 2)/2 = 8.5pF (Refer Datasheet)
UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0 | XT2DRIVE1);
UCSCTL6 |= (XT2DRIVE0);
UCSCTL6 &= ~XT2OFF; // Set XT2 On
UCSCTL6 &= ~XT1OFF; // Set XT1 On
UCSCTL3 = 0x0021; // FLL : REFOCLK and divby2
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG); // Clear XT1 fault flags
}while(UCSCTL7 & (XT2OFFG + XT1LFOFFG)); // Test XT1 fault flag
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x1F00; //Range
UCSCTL1 = 0x50; //Range
UCSCTL2 = 0x1138; // MCLK : 5 Mhz
_delay_ms(100);
// Clock Source Selection :
UCSCTL4 = 0x0054; // ACLK : XT1CLK; SMCLK : XT2CLK; MCLK : DCOCLKDIV
UCSCTL5 |= DIVS1; // SMCLK div by 4 (4 Mhz)
UCSCTL3 |= 0x0021; // FLLRef : REF0; FLLRef/2 => MCLK = 5Mhz
// Enable the FLL control loop
__bic_SR_register(SCG0);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); // Clear XT2,XT1,DCO fault flags; XT1HFOFFG
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while(SFRIFG1 & OFIFG); // Test oscillator fault flag
XT1:32.768 Khz
XT2:16MHz
取决于ACLK的外围设备(因此也取决于XT1)
UART波特率生成
看门狗打断
一旦我进入LPM3,我希望WDT计时器将控制器从深度睡眠中唤醒,但观察到,当我进入LPM3时,XT1立即关闭(也尝试了LPM0),因此控制器从未从睡眠中唤醒
我已经确定的:
UCSCTL6 |= (SMCLKOFF);
_delay_ms(10);
UCSCTL6 |= (XT2OFF);
我确保中断正常工作(在LPM3中)
在以下情况下工作正常
P3SEL |= BIT4; // SMCLK
P3DIR |= BIT4;
P7SEL |= 0x0C; // P7.3,2 -> XT2OUT, XT2IN
// Unlock XT1 pins for operation
while(BAKCTL & LOCKBAK)
{
BAKCTL &= ~(LOCKBAK);
}
// From XT2 = 16 Mhz
UCSCTL6 |= XCAP_2; // Fz 120216: Internal load cap (CAP Value + 2)/2 = 8.5pF (Refer Datasheet)
UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0 | XT2DRIVE1);
UCSCTL6 |= (XT2DRIVE0);
UCSCTL6 &= ~XT2OFF; // Set XT2 On
UCSCTL6 &= ~XT1OFF; // Set XT1 On
UCSCTL3 = 0x0021; // FLL : REFOCLK and divby2
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG); // Clear XT1 fault flags
}while(UCSCTL7 & (XT2OFFG + XT1LFOFFG)); // Test XT1 fault flag
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x1F00; //Range
UCSCTL1 = 0x50; //Range
UCSCTL2 = 0x1138; // MCLK : 5 Mhz
_delay_ms(100);
// Clock Source Selection :
UCSCTL4 = 0x0054; // ACLK : XT1CLK; SMCLK : XT2CLK; MCLK : DCOCLKDIV
UCSCTL5 |= DIVS1; // SMCLK div by 4 (4 Mhz)
UCSCTL3 |= 0x0021; // FLLRef : REF0; FLLRef/2 => MCLK = 5Mhz
// Enable the FLL control loop
__bic_SR_register(SCG0);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); // Clear XT2,XT1,DCO fault flags; XT1HFOFFG
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while(SFRIFG1 & OFIFG); // Test oscillator fault flag
提前感谢。问题解决了。回答我自己的问题,这样别人可能会觉得有用 在我的设计中,VBAT引脚未连接。根据用户手册,未使用时,应将其连接至DVcc 将VBAT连接到DVcc解决了这个问题 我不知道为什么在DVCC未关闭时XT1依赖VBAT电源 无论如何,问题解决了:)