Graphviz 使用群集时的子图位置问题_

我刚刚发现了GraphViz，我正试图根据文档和示例创建一个相当简单的网络图

因此，我尝试将其分为3个主要类别，我希望这3个类别从上到下排列：hypervisor->core->edge

下面的代码非常好，但是如果我尝试将

子图核心

转换为

子图集群_核心

，它会变得有点模糊。突然，

core

向左移动，节点垂直排列（尝试用

rankdir

和

rank=same

覆盖节点）-但我真的想要外部边框和标签！我是不是遗漏了什么？问题在椅子和电脑之间吗

到目前为止，我掌握的代码是：

digraph network {
  graph [overlap = false]

  // Node definitions
  subgraph core {
    rank = same
    labelloc = c
    label = "Core"

    node [shape=square]
      SR_CORE DR_CORE

    node [shape=plaintext]
      ROUTE2 ROUTE1

  }

  subgraph cluster_hypervisors {
    rank = same
    labelloc = c
    style = filled
    label = "Hypervisors"

    node [shape=circle style=filled fillcolor=white]
      NODE01 NODE02 NODE03 NODE04
  }

  subgraph cluster_edge {
    rank = same
    labelloc = c
    label = "Edge"

    node [shape=rectangle]
      SWITCH01 SWITCH02 SWITCH03
  }

  // Edge definitions
  SR_CORE -> ROUTE2 -> DR_CORE [dir=none]
  SR_CORE -> ROUTE1 -> DR_CORE [dir=none]

  SR_CORE -> { SWITCH01 SWITCH02 }
  DR_CORE -> { SWITCH03 }

  NODE01 -> SR_CORE [dir=back]
  NODE02 -> SR_CORE [dir=back]
  NODE03 -> DR_CORE [dir=back]
  NODE04 -> DR_CORE [dir=back]

}

---

必须使用

{}

对

集群_core

中的节点进行分组。要调整外观，您还可以向少数边添加一些

constraint=false

：

digraph network {
  graph [overlap = false]

  // Node definitions
  subgraph cluster_core {
    rank = same
    labelloc = c
    label = "Core"

    node [shape=square]
      SR_CORE DR_CORE

    node [shape=plaintext]
      ROUTE2 ROUTE1

    {SR_CORE DR_CORE ROUTE2 ROUTE1}
  }

  subgraph cluster_hypervisors {
    rank = same
    labelloc = c
    style = filled
    label = "Hypervisors"

    node [shape=circle style=filled fillcolor=white]
      NODE01 NODE02 NODE03 NODE04
  }

  subgraph cluster_edge {
    rank = same
    labelloc = c
    label = "Edge"

    node [shape=rectangle]
      SWITCH01 SWITCH02 SWITCH03
  }

  // Edge definitions
  SR_CORE -> ROUTE2 [dir=none]
  SR_CORE -> ROUTE1 [dir=none, constraint=false]
  ROUTE2 -> DR_CORE [dir=none, constraint=false]
  ROUTE1 -> DR_CORE [dir=none, constraint=false]

  SR_CORE -> { SWITCH01 SWITCH02 }
  DR_CORE -> { SWITCH03 }

  NODE01 -> SR_CORE [dir=back]
  NODE02 -> SR_CORE [dir=back]
  NODE03 -> DR_CORE [dir=back]
  NODE04 -> DR_CORE [dir=back]
}

---

您可以查看上的工作示例

很抱歉，回复延迟，我似乎已停止接收电子邮件中的SO通知，并且有一段时间没有登录。谢谢你的帮助，我不知道我错过了！我现在也看到了边缘约束的力量！