If statement VHDL-比较IF语句中的信号(整数)
我正试图写代码来改变我的时钟频率。但是输出总是零If statement VHDL-比较IF语句中的信号(整数),if-statement,integer,compare,comparison,vhdl,If Statement,Integer,Compare,Comparison,Vhdl,我正试图写代码来改变我的时钟频率。但是输出总是零 signal cycle_counter : integer := 0; signal HALFCYCLES : integer; signal MY_CLK1, temporal : std_logic :='0'; frequency_divider: process (Clk,cycle_counter, HALFCYCLES) begin if rising_edge(Clk) then cycle_coun
signal cycle_counter : integer := 0;
signal HALFCYCLES : integer;
signal MY_CLK1, temporal : std_logic :='0';
frequency_divider: process (Clk,cycle_counter, HALFCYCLES)
begin
if rising_edge(Clk) then
cycle_counter <= cycle_counter + 1;
if cycle_counter = (HALFCYCLES-1) then
temporal <= NOT(temporal);
cycle_counter <= 0;
end if;
end if;
MY_CLK1 <= temporal;
end process frequency_divider;
试验台
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_Std.all;
ENTITY LED_controller_tb IS
END LED_controller_tb;
ARCHITECTURE behavior OF LED_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LED2
PORT(
S : IN std_logic_vector(7 downto 0);
Clk : IN std_logic;
R : IN std_logic;
LED : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal S : std_logic_vector(7 downto 0) := (others => '0');
signal Clk : std_logic := '0';
signal R : std_logic := '0';
--Outputs
signal LED : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LED2 PORT MAP (
S => S,
Clk => Clk,
R => R,
LED => LED
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for Clk_period * 8;
S <= std_logic_vector(to_unsigned(to_integer(unsigned(S)) + 1, 8));
-- insert stimulus here
end process;
reset: PROCESS
BEGIN
WAIT FOR 1 us;
R <= '1';
WAIT FOR 500 ns;
R <= '0';
END PROCESS reset;
END;
ieee库;
使用ieee.std_logic_1164.ALL;
使用ieee.Numeric_Std.all;
实体LED_控制器_tb为
终端LED_控制器_tb;
LED_控制器_tb的架构行为是
--被测单元(UUT)的组件声明
元件LED2
港口(
S:标准逻辑向量(7到0);
Clk:标准逻辑中;
R:在标准逻辑中;
LED:输出标准逻辑向量(7到0)
);
端部元件;
--投入
信号S:std_逻辑_向量(7到0):=(其他=>'0');
信号时钟:标准逻辑:='0';
信号R:std_逻辑:='0';
--输出
信号LED:标准逻辑矢量(7至0);
--时钟周期定义
恒定时钟周期:时间=10纳秒;
开始
--实例化被测单元(UUT)
uut:LED2端口图(
S=>S,
时钟=>Clk,
R=>R,
发光二极管=>发光二极管
);
--时钟进程定义
Clk_流程:流程
开始
Clk我认为你的测试台变化太快了。我在你们的测试台上换了一条线,等了很长一段时间,看起来还可以
根据Andy的建议,我会将您设计的第26行更改为
if cycle_counter >= (HALFCYCLES-1) then --(HALFCYCLES-1)
这是(修改过的)完整的测试台。我还添加了一个进程来停止模拟;否则,它将永远运行:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_Std.all;
ENTITY LED_controller_tb IS
END LED_controller_tb;
ARCHITECTURE behavior OF LED_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LED2
PORT(
S : IN std_logic_vector(7 downto 0);
Clk : IN std_logic;
R : IN std_logic;
LED : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal S : std_logic_vector(7 downto 0) := (others => '0');
signal Clk : std_logic := '0';
signal R : std_logic := '0';
--Outputs
signal LED : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LED2 PORT MAP (
S => S,
Clk => Clk,
R => R,
LED => LED
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for Clk_period * 800; -- WAIT MUCH LONGER BEFORE CHANGING S !
S <= std_logic_vector(to_unsigned(to_integer(unsigned(S)) + 1, 8));
-- insert stimulus here
end process;
reset: PROCESS
BEGIN
WAIT FOR 1 us;
R <= '1';
WAIT FOR 500 ns;
R <= '0';
END PROCESS reset;
STOP_SIM: process -- OTHERWISE THE SIM RUNS FOREVER
begin
wait for Clk_period * 4000;
assert FALSE severity FAILURE;
end process;
END;
ieee库;
使用ieee.std_logic_1164.ALL;
使用ieee.Numeric_Std.all;
实体LED_控制器_tb为
终端LED_控制器_tb;
LED_控制器_tb的架构行为是
--被测单元(UUT)的组件声明
元件LED2
港口(
S:标准逻辑向量(7到0);
Clk:标准逻辑中;
R:在标准逻辑中;
LED:输出标准逻辑向量(7到0)
);
端部元件;
--投入
信号S:std_逻辑_向量(7到0):=(其他=>'0');
信号时钟:标准逻辑:='0';
信号R:std_逻辑:='0';
--输出
信号LED:标准逻辑矢量(7至0);
--时钟周期定义
恒定时钟周期:时间=10纳秒;
开始
--实例化被测单元(UUT)
uut:LED2端口图(
S=>S,
时钟=>Clk,
R=>R,
发光二极管=>发光二极管
);
--时钟进程定义
Clk_流程:流程
开始
Clk看起来您从未分配过半周期
。我建议将其设置为常量,例如:常量半周期:整数:=16代码>我有另一个进程来分配半循环完成示例。比较整数信号是可行的,但如果没有完整的示例,我们只能猜测为什么这里没有。如果不进行模拟:其中一个问题是您使用比较(“=”)作为计数器。当您更改阈值时,可能会发生计数器实际超过阈值的情况。使用“更大或相等”代替。对于ModelSim,它也起作用。至少“暂时性”并没有被任何东西所束缚。除了应用我和Matthew Taylor提到的更改,我什么也没做代码>在重置过程结束时。要停止模拟,只需停止clk\u进程中的时钟
。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_Std.all;
ENTITY LED_controller_tb IS
END LED_controller_tb;
ARCHITECTURE behavior OF LED_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LED2
PORT(
S : IN std_logic_vector(7 downto 0);
Clk : IN std_logic;
R : IN std_logic;
LED : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal S : std_logic_vector(7 downto 0) := (others => '0');
signal Clk : std_logic := '0';
signal R : std_logic := '0';
--Outputs
signal LED : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LED2 PORT MAP (
S => S,
Clk => Clk,
R => R,
LED => LED
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for Clk_period * 800; -- WAIT MUCH LONGER BEFORE CHANGING S !
S <= std_logic_vector(to_unsigned(to_integer(unsigned(S)) + 1, 8));
-- insert stimulus here
end process;
reset: PROCESS
BEGIN
WAIT FOR 1 us;
R <= '1';
WAIT FOR 500 ns;
R <= '0';
END PROCESS reset;
STOP_SIM: process -- OTHERWISE THE SIM RUNS FOREVER
begin
wait for Clk_period * 4000;
assert FALSE severity FAILURE;
end process;
END;