Syntax xilinx中条件信号分配中分配的元素数量不匹配
我在第90行有个错误Syntax xilinx中条件信号分配中分配的元素数量不匹配,syntax,vhdl,xilinx,Syntax,Vhdl,Xilinx,我在第90行有个错误 90 std_logic_vector( unsigned(a)+ unsigned(b) ) when (arth_sel)="0000" else 我的代码是: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Arth is Port (signal arth_sel : in STD_LOGIC_VECTOR (3 downto 0);
90 std_logic_vector( unsigned(a)+ unsigned(b) ) when (arth_sel)="0000" else
我的代码是:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Arth is
Port (signal arth_sel : in STD_LOGIC_VECTOR (3 downto 0);
a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
c : in STD_LOGIC_VECTOR(0 downto 0);
result : out STD_LOGIC_VECTOR (16 downto 0));
end Arth;
architecture Behavioral of Arth is
--das_result : std_logic_vector(15 downto 0);
signal a_lower :std_logic_vector(7 downto 0) := a(7 downto 0);
signal b_lower :std_logic_vector(7 downto 0) := b(7 downto 0);
signal sum_temp1_lower : std_logic_vector(7 downto 0);
signal sum_temp1_upper : std_logic_vector(7 downto 0);
signal sum_temp1 : std_logic_vector(15 downto 0);
signal sum_temp2: std_logic_vector(7 downto 0);
signal daa_result: std_logic_vector(15 downto 0);
begin
sum_temp1 <= std_logic_vector(unsigned(a) + unsigned(b));
sum_temp2 <= std_logic_vector(unsigned(a_lower)+unsigned(b_lower));
sum_temp1_lower <= sum_temp1(7 downto 0);
sum_temp1_upper <= sum_temp1(15 downto 8);
process(a,b)
begin
if ( unsigned(sum_temp1_upper) >9 and unsigned(sum_temp1_lower) >9) then
sum_temp1<= std_logic_vector(unsigned(sum_temp1)+66);
elsif( unsigned(sum_temp1_lower) > 9 or sum_temp2(7)='1') then
sum_temp1 <= std_logic_vector(unsigned(sum_temp1)+6) ;
elsif (unsigned(sum_temp1_upper) > 9) then
sum_temp1<= std_logic_vector(unsigned(sum_temp1)+60);
end if;
daa_result<= sum_temp1;
end process;
result <=
std_logic_vector( unsigned(a)+ unsigned(b) ) when (arth_sel)="0000" else
std_logic_vector( unsigned(a)+ unsigned(b)) when (arth_sel)="0001" else
std_logic_vector( unsigned(a)+ unsigned(b) + unsigned(c)) when (arth_sel)="0010" else
std_logic_vector( unsigned(a)+1)when (arth_sel)="0011" else
std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="0100" else
std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="0101" else
std_logic_vector( unsigned(a)- unsigned(b) - unsigned(c))when (arth_sel)="0110" else
std_logic_vector( unsigned(a)- 1)when (arth_sel)="0111" else
std_logic_vector( unsigned(a)* unsigned(b))when (arth_sel)="1000" else
std_logic_vector( signed(a)* signed(b))when (arth_sel)="1001" else
std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="1010" else
std_logic_vector( unsigned(a)- unsigned(b))when (arth_sel)="1011" else std_logic_vector( unsigned(not(a))+1)when (arth_sel)="1100" else
daa_result when(arth_sel)="1101" else
(others => 'X');
end Behavioral;
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.NUMERIC_STD.ALL;
地球是一个实体
端口(信号接地选择:标准逻辑向量(3向下至0);
a:标准逻辑向量(15到0);
b:标准逻辑向量(15到0);
c:标准逻辑向量(0到0);
结果:输出STD_逻辑_向量(16到0);
结束地球;
阿尔斯的建筑是
--das_结果:标准逻辑向量(15到0);
信号a_lower:std_逻辑_矢量(7向下至0):=a(7向下至0);
信号b_下降:标准逻辑向量(7下降到0):=b(7下降到0);
信号和temp1较低:标准逻辑向量(7到0);
信号和时间上限:标准逻辑向量(7到0);
信号和时间1:标准逻辑向量(15到0);
信号和2:标准逻辑向量(7到0);
信号daa_结果:标准逻辑向量(15到0);
开始
sum_temp1问题在于选择:
result <= ...
daa_result when(arth_sel)="1101" else
具体来说,是范围所暗示的长度
不清楚daa是什么意思,你可以:
'0'& daa_result when(arth_sel)="1101" else
要将长度增加到17,请选择匹配结果
顺便说一下:
signal a_lower :std_logic_vector(7 downto 0) := a(7 downto 0);
signal b_lower :std_logic_vector(7 downto 0) := b(7 downto 0);
不是将a和b的低位8位分别分配给a_lower和b_lower的方法。此默认值分配仅在声明这两个信号时有效,并且将全部为“U”
您可以添加并发信号分配语句:
begin
a_lower <= a(7 downto 0);
b_lower <= b(7 downto 0);
需要一些VHDL技巧:
result <=
std_logic_vector(unsigned(a) + unsigned(b)) when arth_sel = "0000" else
std_logic_vector(unsigned(a) + unsigned(b)) when arth_sel = "0001" else
std_logic_vector(unsigned(a) + unsigned(b)
+ unsigned'(c & "")) when arth_sel = "0010" else
std_logic_vector(unsigned(a) + 1) when arth_sel = "0011" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "0100" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "0101" else
std_logic_vector(unsigned(a) - unsigned(b)
- unsigned'(c & "")) when arth_sel = "0110" else
std_logic_vector(unsigned(a) - 1) when arth_sel = "0111" else
std_logic_vector(unsigned(a) * unsigned(b)) when arth_sel = "1000" else
std_logic_vector(signed(a) * signed(b)) when arth_sel = "1001" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "1010" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "1011" else
std_logic_vector(unsigned(not(a))+1) when arth_sel = "1100" else
'0' & daa_result when arth_sel = "1101" else
(others => 'X');
结果“X”);
其中unsigned'(c&“”)
将c
与长度为零的字符串连接起来,并将生成的数组类型限定为unsigned
c: in std_logic; -- _vector (0 downto 0);
result <=
std_logic_vector(unsigned(a) + unsigned(b)) when arth_sel = "0000" else
std_logic_vector(unsigned(a) + unsigned(b)) when arth_sel = "0001" else
std_logic_vector(unsigned(a) + unsigned(b)
+ unsigned'(c & "")) when arth_sel = "0010" else
std_logic_vector(unsigned(a) + 1) when arth_sel = "0011" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "0100" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "0101" else
std_logic_vector(unsigned(a) - unsigned(b)
- unsigned'(c & "")) when arth_sel = "0110" else
std_logic_vector(unsigned(a) - 1) when arth_sel = "0111" else
std_logic_vector(unsigned(a) * unsigned(b)) when arth_sel = "1000" else
std_logic_vector(signed(a) * signed(b)) when arth_sel = "1001" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "1010" else
std_logic_vector(unsigned(a) - unsigned(b)) when arth_sel = "1011" else
std_logic_vector(unsigned(not(a))+1) when arth_sel = "1100" else
'0' & daa_result when arth_sel = "1101" else
(others => 'X');