Vhdl FPGA spartan 3-X mod 3内部无时钟组合进程
我正在从事一个项目，其中一部分围绕着使用FPGA和spartan 3（Xilinx）查找X mod 3， 在组合过程中。 事实上，在这个项目中，在这个ALU模块之前，还有一些其他的模块是顺序的。 但在ALU模块内部，不允许使用顺序过程。 因此，我尝试使用以下一种方法： 这里有一个简单的手工方法。因为1=22模3，我们得到1= 22n mod 3表示每个正整数。此外，2=22n+1模3。 因此，我们可以通过计数来确定一个整数是否可以被3整除 奇数位位置的1位乘以2，将 偶数位位置的1位数将它们添加到结果中，然后 检查结果是否可以被3整除 示例：5710=1110012。奇数位置有2位，2位 在相同的位置。2*2+2=6可被3整除。因此57是 可以被3整除 我已经把我的密码贴在那里了。问题是，在我将两个不同信号中的奇数位和偶数位串联在一起之后：Vhdl FPGA spartan 3-X mod 3内部无时钟组合进程,vhdl,fpga,modelsim,xilinx-ise,Vhdl,Fpga,Modelsim,Xilinx Ise,我正在从事一个项目，其中一部分围绕着使用FPGA和spartan 3（Xilinx）查找X mod 3， 在组合过程中。 事实上，在这个项目中，在这个ALU模块之前，还有一些其他的模块是顺序的。 但在ALU模块内部，不允许使用顺序过程。 因此，我尝试使用以下一种方法： 这里有一个简单的手工方法。因为1=22模3，我们得到1= 22n mod 3表示每个正整数。此外，2=22n+1模3。 因此，我们可以通过计数来确定一个整数是否可以被3整除 奇数位位置的1位乘以2，将 偶数位位置的1位数将它们添加
mod_un_t1 <= A(6) & A(4)& A(2) & A(0);
mod_un_t2 <= A(7) & A(5)& A(3) & A(1);
mod_un_t1过程灵敏度列表中缺少似乎没有分配的信号。否则，它们可能是变量，允许在当前模拟周期中使用，而不生成增量周期，因为信号分配直到结束或当前模拟周期才生效
变量的候选项似乎是：
signal mod_un_t1: std_logic_vector (3 downto 0);
signal mod_un_t2: std_logic_vector (3 downto 0);
signal mod_un_t3: std_logic_vector (3 downto 0);
signal mod_un_t4: std_logic_vector (3 downto 0);
signal mod_unsigned: std_logic_vector (3 downto 0);
signal mod_si_t1: std_logic_vector (3 downto 0);
signal mod_si_t2: std_logic_vector (3 downto 0);
signal mod_si_t3: std_logic_vector (3 downto 0);
signal mod_si_t4: std_logic_vector (3 downto 0);
signal mod_signed: std_logic_vector (3 downto 0);
这些声明可以更改为对象类变量并移动到流程中（在开始之前）。他们的信号分配（@David Koontz，你的回答给出了我所需要的结果。非常感谢。这真的是一个很大的帮助。顺便说一句，这个结果是我设计的ALU中的另一个算术运算。@David Koontz，你能不能也给出一个简短的例子，说明如何将进程分解为多个进程和/或其他并发语句？请注意，你没有“在if语句条件中，二进制值没有完全覆盖，这意味着推断的锁存。我应该怎么做？您的意思是我最好选择when/case或when/select，还是我应该为结果指定一个伪值，并在所有if语句的末尾添加一个else？”？？
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Use Ieee.std_logic_unsigned.all;
entity ALU is
port ( A : in std_logic_vector (7 downto 0); -- Input A
B : in std_logic_vector (7 downto 0); -- Input B
FN : in std_logic_vector (3 downto 0); -- ALU functions provided by the ALU_Controller (see the lab manual)
result : out std_logic_vector (7 downto 0); -- ALU output (unsigned binary)
overflow : out std_logic; -- '1' if overflow ocurres, '0' otherwise
sign : out std_logic -- '1' if the result is a negative value, '0' otherwise
);
end ALU;
architecture behavioral of ALU is
signal mod_un_t1: std_logic_vector (3 downto 0);
signal mod_un_t2: std_logic_vector (3 downto 0);
signal mod_un_t3: std_logic_vector (3 downto 0);
signal mod_un_t4: std_logic_vector (3 downto 0);
signal mod_unsigned: std_logic_vector (3 downto 0);
signal mod_si_t1: std_logic_vector (3 downto 0);
signal mod_si_t2: std_logic_vector (3 downto 0);
signal mod_si_t3: std_logic_vector (3 downto 0);
signal mod_si_t4: std_logic_vector (3 downto 0);
signal mod_signed: std_logic_vector (3 downto 0);
begin
process ( FN, A, B , result_tmp)
begin
result <= (others => '0');
mod_un_t1 <= (others => '0');
mod_un_t2 <= (others => '0');
mod_un_t3 <= (others => '0');
mod_un_t4 <= (others => '0');
mod_unsigned <= (others => '0');
mod_si_t1 <= (others => '0');
mod_si_t2 <= (others => '0');
mod_si_t3 <= (others => '0');
mod_si_t4 <= (others => '0');
mod_signed <= (others => '0');
if (FN = "0100") then -- Unsigned (A) mod 3
mod_un_t1 <= A(6) & A(4)& A(2) & A(0);
mod_un_t2 <= A(7) & A(5)& A(3) & A(1);
if(mod_un_t1= "1111") then
mod_un_t3 <= "1000";
elsif(mod_un_t1 = "1110" or mod_un_t1 = "1101" or mod_un_t1 = "1011" or mod_un_t1 = "0111") then
mod_un_t3 <= "0110";
elsif(mod_un_t1 = "1100" or mod_un_t1 = "1010" or mod_un_t1 = "1001" or mod_un_t1 = "0110" or mod_un_t1 = "0101" or mod_un_t1 = "0011") then
mod_un_t3 <= "0100";
elsif(mod_un_t1 = "0001" or mod_un_t1 = "0010" or mod_un_t1 = "0100" or mod_un_t1 = "1000") then
mod_un_t3 <= "0010";
elsif (mod_un_t1 = "0000") then
mod_un_t3 <= "0000";
end if;
if (mod_un_t2 = "1111") then
mod_un_t4 <= "0100";
elsif (mod_un_t2 = "1110" or mod_un_t2 = "1101" or mod_un_t2 = "1011" or mod_un_t2 = "0111") then
mod_un_t4 <= "0011";
elsif(mod_un_t2 = "1100" or mod_un_t2 = "1010" or mod_un_t2 = "1001" or mod_un_t2 = "0110" or mod_un_t2 = "0101" or mod_un_t2 = "0011") then
mod_un_t4 <= "0010";
elsif(mod_un_t2 = "0001" or mod_un_t2 = "0010" or mod_un_t2 = "0100" or mod_un_t2 = "1000") then
mod_un_t4 <= "0001";
elsif(mod_un_t2 = "0000") then
mod_un_t4 <= "0000";
end if;
mod_unsigned <= mod_un_t3 + mod_un_t4;
if (mod_unsigned = "0010" or mod_unsigned = "0101" or mod_unsigned ="0111" or mod_unsigned = "1010") then
result <= "00000001";
elsif (mod_unsigned = "0001" or mod_unsigned = "0100" or mod_unsigned = "1000" or mod_unsigned = "1011") then
result <= "00000010";
elsif (mod_unsigned = "0000" or mod_unsigned = "0011" or mod_unsigned = "0110" or mod_unsigned = "1001") then
result <= "00000000";
end if;
end if;
end process;
end behavioral;
signal mod_un_t1: std_logic_vector (3 downto 0);
signal mod_un_t2: std_logic_vector (3 downto 0);
signal mod_un_t3: std_logic_vector (3 downto 0);
signal mod_un_t4: std_logic_vector (3 downto 0);
signal mod_unsigned: std_logic_vector (3 downto 0);
signal mod_si_t1: std_logic_vector (3 downto 0);
signal mod_si_t2: std_logic_vector (3 downto 0);
signal mod_si_t3: std_logic_vector (3 downto 0);
signal mod_si_t4: std_logic_vector (3 downto 0);
signal mod_signed: std_logic_vector (3 downto 0);
Aarchitecture foo of ALU is
signal mod_un_t1: std_logic_vector (3 downto 0);
signal mod_un_t2: std_logic_vector (3 downto 0);
signal mod_un_t3: std_logic_vector (3 downto 0);
signal mod_un_t4: std_logic_vector (3 downto 0);
signal mod_unsigned: std_logic_vector (3 downto 0);
signal mod_si_t1: std_logic_vector (3 downto 0);
signal mod_si_t2: std_logic_vector (3 downto 0);
signal mod_si_t3: std_logic_vector (3 downto 0);
signal mod_si_t4: std_logic_vector (3 downto 0);
signal mod_signed: std_logic_vector (3 downto 0);
-- dummy
signal result_tmp: std_logic_vector(7 downto 0);
begin
-- Concurrent signal assignments - these are just wires
mod_un_t1 <= A(6) & A(4)& A(2) & A(0);
mod_un_t2 <= A(7) & A(5)& A(3) & A(1);
UNPROC1:
process (FN, mod_un_t1)
begin
if FN = "0100" then
case mod_un_t1 is
when "0000" =>
mod_un_t3 <= "0000";
when "0001" | "0010" | "0100" | "1000" =>
mod_un_t3 <= "0010";
when "1100" | "1010" | "1001" | "0110" =>
mod_un_t3 <= "0100";
when "1110" | "1101" | "1011" | "0111" =>
mod_un_t3 <= "0100";
when others =>
end case;
else
--
end if;
end process;
UNPROC2:
process (FN, mod_un_t2)
begin
if FN = "0100" then
if mod_un_t2 = "1111" then
mod_un_t4 <= "0100";
elsif mod_un_t2 = "1110" or mod_un_t2 = "1101" or mod_un_t2 = "1011" or mod_un_t2 = "0111" then
mod_un_t4 <= "0011";
elsif mod_un_t2 = "1100" or mod_un_t2 = "1010" or mod_un_t2 = "1001" or mod_un_t2 = "0110" or mod_un_t2 = "0101" or mod_un_t2 = "0011" then
mod_un_t4 <= "0010";
elsif mod_un_t2 = "0001" or mod_un_t2 = "0010" or mod_un_t2 = "0100" or mod_un_t2 = "1000" then
mod_un_t4 <= "0001";
elsif mod_un_t2 = "0000" then
mod_un_t4 <= "0000";
end if;
else
--
end if;
end process;
ALU_PROC: -- keep all the arithemetic operations in one process
process (FN, mod_un_t3, mod_un_t4)
begin
if FN = "0100" then
mod_unsigned <= mod_un_t3 + mod_un_t4;
else
end if;
end process;
OUT_PROC: -- keep all the result assignment in one process
process (FN, mod_unsigned)
begin
if FN = "0100" then
if mod_unsigned = "0010" or mod_unsigned = "0101" or mod_unsigned ="0111" or mod_unsigned = "1010" then
result <= "00000001";
elsif mod_unsigned = "0001" or mod_unsigned = "0100" or mod_unsigned = "1000" or mod_unsigned = "1011" then
result <= "00000010";
elsif mod_unsigned = "0000" or mod_unsigned = "0011" or mod_unsigned = "0110" or mod_unsigned = "1001" then
result <= "00000000";
else
--
end if;
end if;
end process;
end architecture foo;