System verilog Systemverilog断言检查错误信号转换

我试图写一个断言，只有当信号在“clk”的上升沿上转换时才会触发。我写了下面的代码来测试我的想法

module test();

bit clk, clkb;
int d;

assign clkb = ~clk;

initial begin
   clk = 0;
   forever #100 clk = ~clk;
end

initial begin
   d = 10;
   #150 d = 20;
end

sva_d_chgd: assert property (@(posedge clk) $stable(d,@(clkb))) 
   else $error($psprintf("err: time = %0d, clk = %b, d = %0d", $time, clk, d));

always @ (d or clk) begin
   $display("time = %0d, clk = %b, d = %0d", $time, clk, d);
   if ($time > 200) $finish;
end
endmodule

上述代码返回VCS中的以下输出：

time = 0, clk = 0, d = 10
time = 100, clk = 1, d = 10
"test.vs", 18: test.sva_d_chgd: started at 100s failed at 100s
        Offending '$stable(d, @(clkb))'
Error: "test.vs", 18: test.sva_d_chgd: at time 100
err: time = 100, clk = 1, d = 10
time = 150, clk = 1, d = 20
time = 200, clk = 0, d = 20
time = 300, clk = 1, d = 20
$finish called from file "test.vs", line 23.
$finish at simulation time                  300

---

为什么断言在时间100触发，而“d”在时间150之前保持稳定

在您的代码中，stable在clk的每个posedge处检查“d”的值在clkb的前两个边之间是否发生了变化。因为在clk的第一个posedge上没有以前的clkb edge值“d”，所以stable返回“unknown”而不是“true”或“false”，这会导致断言失败

我在代码中添加了一个重置信号，并在clk的第一个posedge之后禁用了断言。当“d”改变时，我也移动了

以下是输出：

# time = 0, clk = 0, d = 10
# time = 100, clk = 1, d = 10
# time = 200, clk = 0, d = 10
# time = 250, clk = 0, d = 20
# time = 300, clk = 1, d = 20
# ** Error: err: time = 300, clk = 1, d = 20
#    Time: 300 ns Started: 300 ns  Scope: test.sva_d_chgd File: assert_test.sv Line: 26
# time = 400, clk = 0, d = 20
# time = 500, clk = 1, d = 20
# ** Note: $finish    : assert_test.sv(30)
#    Time: 500 ns  Iteration: 1  Instance: /test

---

这绕过了断言的第一次意外失败，但我认为您编写断言的方式仍然没有真正捕获您正在寻找的条件。

感谢您指出重置问题，但为什么断言仍然错误触发？在时间300时，d仍然是值20，那么为什么断言会触发呢？您正在每个posedge clk上评估您的断言。在300ns（posedge clk）时，“d”在250ns处发生了变化，这在clkb的200ns和300ns边缘之间，因此您的断言被评估为false。有道理吗？是的，有道理。关于$stable是如何工作的，我错了

# time = 0, clk = 0, d = 10
# time = 100, clk = 1, d = 10
# time = 200, clk = 0, d = 10
# time = 250, clk = 0, d = 20
# time = 300, clk = 1, d = 20
# ** Error: err: time = 300, clk = 1, d = 20
#    Time: 300 ns Started: 300 ns  Scope: test.sva_d_chgd File: assert_test.sv Line: 26
# time = 400, clk = 0, d = 20
# time = 500, clk = 1, d = 20
# ** Note: $finish    : assert_test.sv(30)
#    Time: 500 ns  Iteration: 1  Instance: /test