Text VHDL-将标准逻辑向量移位8位
既然我已经成功地在写作时移动了文本,我想实现另一个功能,每秒滚动文本1位。例如,我将从键盘上写下“堆栈”,然后当我切换一个管脚时,它将开始在七段显示器上浮动。我得到了多个时钟错误,正如我所预料的。现在,我用计数器克服了这个错误,但是文本没有正确滚动,随机字符出现在随机位置Text VHDL-将标准逻辑向量移位8位,text,scroll,vhdl,clock,shift,Text,Scroll,Vhdl,Clock,Shift,既然我已经成功地在写作时移动了文本,我想实现另一个功能,每秒滚动文本1位。例如,我将从键盘上写下“堆栈”,然后当我切换一个管脚时,它将开始在七段显示器上浮动。我得到了多个时钟错误,正如我所预料的。现在,我用计数器克服了这个错误,但是文本没有正确滚动,随机字符出现在随机位置 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.all; entity my_
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
entity my_shifter is
port(clk : in std_logic;
doShift : in std_logic;--shift mode
Scan_Dav : in std_logic;--from keyboard module, new data
Data_in : in std_logic_vector (7 downto 0);--scancode of the key pressed
O1 : out std_logic_vector(7 downto 0);
O2 : out std_logic_vector(7 downto 0);
O3 : out std_logic_vector(7 downto 0);
O4 : out std_logic_vector(7 downto 0)
);
end my_shifter;
architecture bhv of my_shifter is
signal bytes : std_logic_vector(63 downto 0):=(others => '0');
signal Scan_Dav_Sync: std_logic_vector(1 downto 0):="00";
signal Previous_Scan_Dav: std_logic:='0';
signal shift : std_logic:='0';
signal flag : std_logic:='0';
signal first_letter: std_logic_vector(7 downto 0):="00000000";
begin
process(clk)
variable var:integer range 0 to 50000000 :=0;
begin
if rising_edge(clk) then
if var = 50000000 then
var:=0;
flag<='0';
shift <= '1';
else
flag <= '1';
var:=var+1;
shift <= '0';
end if;
end if;
end process;
process (clk, doShift)
begin
case doShift is
when '0' =>
if rising_edge(clk) then
Scan_Dav_Sync(0) <= Scan_Dav;
Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
Previous_Scan_Dav <= Scan_Dav_Sync(1);
if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
end if;--till here it works fine.
when '1' => -- this is where it messes up
if (shift = '1' and flag = '0' ) then
first_letter <= bytes(bytes'high downto bytes'high-7);
bytes <= bytes (bytes'high-8 downto 0) & first_letter;
end if;
when others =>--ignore here
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end case;
end process;
O1 <= bytes(31 downto 24);
O2 <= bytes(23 downto 16);
O3 <= bytes(15 downto 8);
O4 <= bytes(7 downto 0);
end bhv;
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.STD_LOGIC_UNSIGNED.ALL;
使用IEEE.numeric_std.all;
实体我的移位器是
端口(时钟:在标准逻辑中;
doShift:在std_逻辑中;--移位模式
扫描Dav:在标准逻辑中;--来自键盘模块,新数据
数据输入:标准逻辑向量(7到0);--按键的扫描码
O1:输出标准逻辑向量(7到0);
O2:输出标准逻辑向量(7到0);
O3:输出标准逻辑向量(7到0);
O4:输出标准逻辑向量(7到0)
);
结束我的移动;
我的换档杆的结构bhv为
信号字节:标准逻辑向量(63到0):=(其他=>'0');
信号扫描同步:标准逻辑向量(1到0):=“00”;
信号上一次扫描数据:标准逻辑:='0';
信号移位:标准逻辑:='0';
信号标志:标准逻辑:='0';
信号第一个字母:标准逻辑向量(7到0):=“00000000”;
开始
过程(clk)
变量var:整数范围0到50000000:=0;
开始
如果上升沿(clk),则
如果var=50000000,则
var:=0;
flag如果您将第二个进程设置为一个正常的时钟进程,则最有可能不受此影响
比如:
process (clk)
begin
if rising_edge(clk) then
case doShift is
when '0' =>
Scan_Dav_Sync(0) <= Scan_Dav;
Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
Previous_Scan_Dav <= Scan_Dav_Sync(1);
if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
when '1' =>
if (shift = '1' and flag = '0' ) then
first_letter <= bytes(bytes'high downto bytes'high-7);
bytes <= bytes (bytes'high-8 downto 0) & first_letter;
end if;
when others =>
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end case;
end if;
end process;
过程(clk)
开始
如果上升沿(clk),则
案例doShift为
当“0”=>
扫描\u Dav\u Sync(0)遵循时钟进程的建议模式。感谢您的回答,我已经完成了我的设计,它正常工作:)