Variables 计数器溢出或条件不是肉
我正在CoolRunner 2上做一个60分钟计时器的小项目。我想驾驶四个7段显示器来发展我在VHDL方面的新技能，我主要是一名模拟工程师，所以如果你有任何关于VHDL方面的建议，我会乐于接受。但我的问题是：我有四个计数器，它们一起计数到59分59秒，然后重置，但我的第三个计数器不递增（Variables 计数器溢出或条件不是肉,variables,case,vhdl,Variables,Case,Vhdl,我正在CoolRunner 2上做一个60分钟计时器的小项目。我想驾驶四个7段显示器来发展我在VHDL方面的新技能，我主要是一名模拟工程师，所以如果你有任何关于VHDL方面的建议，我会乐于接受。但我的问题是：我有四个计数器，它们一起计数到59分59秒，然后重置，但我的第三个计数器不递增（counter3）。当我运行测试台时，它只会运行59秒，然后重置 下面我附上了我的计数器1,2,3,4的计数器代码。有人能看到拼写错误或明显的错误吗 --counter1---------------------
counter3--counter1-------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow4 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter1 <=0;
elsif Rising_edge (CLK1Hz)then
if (SW1 = '1' ) then
counter1 <= counter1 + 1;
if Counter1 = 8 then
overflow1 <= '1';
elsif counter1 = 9 then
Counter1 <= 0;
overflow1 <= '0';
end if;
end if;
end if;
end process;
--counter2---------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow1,overflow4,counter1 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter2 <=0;
elsif Rising_edge (CLK1Hz) then
if (SW1 = '1' ) and (overflow1 = '1') then
counter2 <= counter2 + 1;
if counter2 = 5 and counter1 = 8 then
overflow2 <= '1';
elsif counter2 = 5 and counter1 = 9 then
counter2 <= 0;
overflow2 <= '0';
end if;
end if;
end if;
end process;
--counter3----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter3 <=0;
elsif Rising_edge (CLK1Hz) then
if (SW1 = '1' ) and (overflow2 = '1') then
counter3 <= counter3 + 1;
if counter3 = 9 and counter2 = 5 and counter1 = 8 then
overflow3 <= '1';
elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then
counter3 <= 0;
overflow3 <= '0';
end if;
end if;
end if;
end process;
--counter4----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter4 <=0;
elsif Rising_edge (CLK1Hz) then
if(SW1 = '1' ) and (overflow3 = '1') then
counter4 <= counter4 + 1;
if counter4 = 6 then
counter4 <= 0;
overflow4 <= '1';
else overflow4 <= '0';
end if;
end if;
end if;
end process;
--计数器1-------------------------------------------
过程（CLK1Hz、RST、SW1、溢流4）
开始
如果（RST='0'）或（溢出4='1'），则
计数器1计数器3没有递增，因为overflow2
从未设置为“1”。让我们看一下代码<时钟>同步部分的处理程序>反2<代码>：
if (SW1 = '1' ) and (overflow1 = '1') then
counter2 <= counter2 + 1;
if counter2 = 5 and counter1 = 8 then
overflow2 <= '1';
elsif counter2 = 5 and counter1 = 9 then
counter2 <= 0;
overflow2 <= '0';
end if;
end if;
这同样适用于计数器3
和计数器4
的过程
在最后一个过程中，只能设置信号溢出4
，因为一旦设置，异步复位将永远执行。如前所述，只需使用计数器4的同步复位<代码>溢出4library ieee;
use ieee.std_logic_1164.all;
entity counter2 is
end entity counter2;
architecture counter2 of counter2 is
signal counter1, counter2, counter3, counter4 : integer := 0;
signal overflow1, overflow2, overflow3, overflow4 : std_logic := '0';
signal RST : std_logic := '1';
signal SW1 : std_logic := '1';
signal CLK1Hz : std_logic := '1';
begin -- architecture counter2
-- clock generation
CLK1Hz <= not CLK1Hz after 500 ms;
--counter1-------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow4 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter1 <=0;
elsif Rising_edge (CLK1Hz)then
if (SW1 = '1' ) then
counter1 <= counter1 + 1;
if Counter1 = 8 then
overflow1 <= '1';
elsif counter1 = 9 then
Counter1 <= 0;
overflow1 <= '0';
end if;
end if;
end if;
end process;
--counter2---------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow1,overflow4,counter1 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter2 <=0;
elsif Rising_edge (CLK1Hz) then
if (SW1 = '1' ) then
if (overflow1 = '1') then
counter2 <= counter2 + 1;
end if;
if counter2 = 5 and counter1 = 8 then
overflow2 <= '1';
elsif counter2 = 5 and counter1 = 9 then
counter2 <= 0;
overflow2 <= '0';
end if;
end if;
end if;
end process;
--counter3----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter3 <=0;
elsif Rising_edge (CLK1Hz) then
if (SW1 = '1' ) then
if (overflow2 = '1') then
counter3 <= counter3 + 1;
end if;
if counter3 = 9 and counter2 = 5 and counter1 = 8 then
overflow3 <= '1';
elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then
counter3 <= 0;
overflow3 <= '0';
end if;
end if;
end if;
end process;
--counter4----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3 )
begin
if (RST = '0') then-- or (overflow4 = '1') then
Counter4 <=0;
elsif Rising_edge (CLK1Hz) then
if(SW1 = '1' ) then
if (overflow3 = '1') then
counter4 <= counter4 + 1;
end if;
if counter4 = 6 then
counter4 <= 0;
overflow4 <= '1';
else overflow4 <= '0';
end if;
end if;
end if;
end process;
end architecture counter2;
ieee库；
使用ieee.std_logic_1164.all；
实体计数器2是
终端实体计数器2；
counter2的架构counter2是
信号计数器1、计数器2、计数器3、计数器4：整数=0；
信号溢出1、溢出2、溢出3、溢出4:std_逻辑：='0'；
信号RST:std_逻辑：='1'；
信号SW1:std_逻辑：='1'；
信号CLK1Hz:std_逻辑：='1'；
开始——架构计数器2
--时钟生成
CLK1Hz计数器3没有递增，因为overflow2
从未设置为“1”。让我们看一下代码<时钟>同步部分的处理程序>反2<代码>：
if (SW1 = '1' ) and (overflow1 = '1') then
counter2 <= counter2 + 1;
if counter2 = 5 and counter1 = 8 then
overflow2 <= '1';
elsif counter2 = 5 and counter1 = 9 then
counter2 <= 0;
overflow2 <= '0';
end if;
end if;
这同样适用于计数器3
和计数器4
的过程
在最后一个过程中，只能设置信号溢出4
，因为一旦设置，异步复位将永远执行。如前所述，只需使用计数器4的同步复位<代码>溢出4library ieee;
use ieee.std_logic_1164.all;
entity counter2 is
end entity counter2;
architecture counter2 of counter2 is
signal counter1, counter2, counter3, counter4 : integer := 0;
signal overflow1, overflow2, overflow3, overflow4 : std_logic := '0';
signal RST : std_logic := '1';
signal SW1 : std_logic := '1';
signal CLK1Hz : std_logic := '1';
begin -- architecture counter2
-- clock generation
CLK1Hz <= not CLK1Hz after 500 ms;
--counter1-------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow4 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter1 <=0;
elsif Rising_edge (CLK1Hz)then
if (SW1 = '1' ) then
counter1 <= counter1 + 1;
if Counter1 = 8 then
overflow1 <= '1';
elsif counter1 = 9 then
Counter1 <= 0;
overflow1 <= '0';
end if;
end if;
end if;
end process;
--counter2---------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow1,overflow4,counter1 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter2 <=0;
elsif Rising_edge (CLK1Hz) then
if (SW1 = '1' ) then
if (overflow1 = '1') then
counter2 <= counter2 + 1;
end if;
if counter2 = 5 and counter1 = 8 then
overflow2 <= '1';
elsif counter2 = 5 and counter1 = 9 then
counter2 <= 0;
overflow2 <= '0';
end if;
end if;
end if;
end process;
--counter3----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2 )
begin
if (RST = '0') or (overflow4 = '1') then
Counter3 <=0;
elsif Rising_edge (CLK1Hz) then
if (SW1 = '1' ) then
if (overflow2 = '1') then
counter3 <= counter3 + 1;
end if;
if counter3 = 9 and counter2 = 5 and counter1 = 8 then
overflow3 <= '1';
elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then
counter3 <= 0;
overflow3 <= '0';
end if;
end if;
end if;
end process;
--counter4----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3 )
begin
if (RST = '0') then-- or (overflow4 = '1') then
Counter4 <=0;
elsif Rising_edge (CLK1Hz) then
if(SW1 = '1' ) then
if (overflow3 = '1') then
counter4 <= counter4 + 1;
end if;
if counter4 = 6 then
counter4 <= 0;
overflow4 <= '1';
else overflow4 <= '0';
end if;
end if;
end if;
end process;
end architecture counter2;
ieee库；
使用ieee.std_logic_1164.all；
实体计数器2是
终端实体计数器2；
counter2的架构counter2是
信号计数器1、计数器2、计数器3、计数器4：整数=0；
信号溢出1、溢出2、溢出3、溢出4:std_逻辑：='0'；
信号RST:std_逻辑：='1'；
信号SW1:std_逻辑：='1'；
信号CLK1Hz:std_逻辑：='1'；
开始——架构计数器2
--时钟生成
CLK1Hz请格式化并缩进您的代码。希望这能帮助您进一步理解我的代码。我建议您编写一个带启用输入和溢出输出的5/9模计数器。然后您可以将此计数器的多个实例链接在一起。在担心Coolrunner之前，让它在模拟中正常工作。嗨，Matin Z，我很快就会拿起笔和纸，试着画出来，写一个psudo代码，看看我是否能让计数器自己工作。请格式化并缩进你的代码。希望这能帮助你更多地理解我的代码。我建议写一个计数器模5/9，带有启用输入和溢出输出。然后你可以将这个计数器的多个实例链接在一起。在担心Coolrunner之前，让它在模拟中正常工作。嗨，Matin Z，我会抓起笔和纸，试着画出来并为它写一个psudo代码，看看我是否能让计数器自己工作。嗨，谢谢你的回复和所有的错误更正，你真好。我在几周前完成了这个项目，和你差不多。我也意识到，当我在做测试台时，我的嵌套如果做得不正确，它几乎没有时间执行。回到VHDL，这是一个有趣的项目。再次感谢您仔细阅读了答案。我希望其他人也能从中受益。嗨，谢谢你的回复和所有的错误更正，你真好。我在几周前完成了这个项目，和你差不多。我也意识到，当我在做测试台时，我的嵌套如果做得不正确，它几乎没有时间执行。回到VHDL，这是一个有趣的项目。再次感谢您仔细阅读了答案。我希望其他人也能从中受益。