Vector 如何强制输入和向量数组

有人知道如何输入或强制输入向量数组吗？我相信是这样的，但它不起作用

--------- Test Bench ---------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use work.mypackage2.all;

ENTITY test_bench IS
PORT (H   : in  enter_vector := ("1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101");
      L   : in  enter_vector := ("1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101");
        X   : out integer);
END entity;
ARCHITECTURE comportamento OF test_bench IS



COMPONENT MUX is
    Port ( SEL : in  STD_LOGIC;
           H   : in  enter_vector;
           L   : in  enter_vector;
           X   : out enter_vector;
              Sinal: out std_logic -- it is 1 if H and 0 if L
              );
END COMPONENT;


COMPONENT choose is
    Port ( SEL : in  STD_LOGIC;
           E   : in  enter_vector;
           X    : out integer);
END COMPONENT;

signal VC : enter_vector;
signal sin,sel: std_logic; 



BEGIN

m:  MUX PORT MAP (sel,H,L,VC,sin);
cc: choose PORT MAP (sin,VC,X);




END comportamento;

------- Type Created-----

    library IEEE; 
    use IEEE.STD_LOGIC_1164.all; 

    package mypackage2 is 

              type enter_vector is array (15 to 0) of std_logic_vector(3 downto 0); -- array of bytes 

    end mypackage2; 


    package body mypackage2 is 

    end mypackage2; 

与此相反：

type enter_vector is array (15 to 0) of std_logic_vector(3 downto 0);
--                              ^
--                              |

你需要这个：

type enter_vector is array (15 downto 0) of std_logic_vector(3 downto 0);
--                                ^
--                                |

---

这在VHDL中是一个令人讨厌的“陷阱”。使用

to

而不是

downto

不是错误，但最终得到的数组长度为0。这通常会导致代码中其他地方出现其他错误。

可以，但这不是我的问题。我的问题在这行：H:in enter_vector:=（“1100”，“0011”，“1111”，“1100”，“0011”，“1111”，“1101”，“1100”，“0011”，“1111”，“1101”，“1100”，“0011”，“0011”，“1111”，“1101”）；L:在enter_vector:=（“1100”、“0011”、“1111”、“1101”、“1100”、“0011”、“1101”、“1100”、“0011”、“1111”、“1101”、“1100”、“0011”、“1111”、“1101”）@matheusasso如前所述，错误消息抛出了该行，但您的问题在您的包中。我更正了它，它编译得很好：。什么错误消息？OP或您不提供。@user1155120

COMP96错误COMP96\u 0127：“聚合长度不正确。预期长度为0。”“testbench.vhd”7 33

除了声明类型enter\u vector以定义空数组外（IEEE Std 1078-2008 5.3.2.2索引约束和离散范围）使用

to

而不是

downto

时，您的问题不会显示出问题。一个港口的实际（6.5.6.3港口条款）需要相同的类型。假设您的代码将进行分析，而

H

和

L

不携带任何信息。你的问题没有提供答案。