SystemVerilog:S-R闩锁不工作';我不能正常工作
以下是我对S-R闩锁的门级描述:SystemVerilog:S-R闩锁不工作';我不能正常工作,verilog,system-verilog,digital-logic,flip-flop,Verilog,System Verilog,Digital Logic,Flip Flop,以下是我对S-R闩锁的门级描述: module SR_Latch_Nand(input S, R, C, output Q, QB); wire s1, r1; nand #8 n1(r1, R, C); nand #8 n2(s1, S, C); nand #8 n3(QB, R, Q); nand #8 n4(Q, S, QB); endmodule module SR_Latch_Nand_TB(); logic s, r, clk; wire q, qb;
module SR_Latch_Nand(input S, R, C, output Q, QB);
wire s1, r1;
nand #8 n1(r1, R, C);
nand #8 n2(s1, S, C);
nand #8 n3(QB, R, Q);
nand #8 n4(Q, S, QB);
endmodule
module SR_Latch_Nand_TB();
logic s, r, clk;
wire q, qb;
SR_Latch_Nand sr(s, r, clk, q, qb);
initial begin
s = 0; r = 0; clk = 0;
#100 s = 1;
#100 clk = 1;
#100 clk = 0;
#100 clk = 1;
#100 s = 0;
#100;
end
endmodule
这是S-R闩锁的测试台:
module SR_Latch_Nand(input S, R, C, output Q, QB);
wire s1, r1;
nand #8 n1(r1, R, C);
nand #8 n2(s1, S, C);
nand #8 n3(QB, R, Q);
nand #8 n4(Q, S, QB);
endmodule
module SR_Latch_Nand_TB();
logic s, r, clk;
wire q, qb;
SR_Latch_Nand sr(s, r, clk, q, qb);
initial begin
s = 0; r = 0; clk = 0;
#100 s = 1;
#100 clk = 1;
#100 clk = 0;
#100 clk = 1;
#100 s = 0;
#100;
end
endmodule
当我检查波形时,Q的值大多数时候是X。其他时候,这基本上是不正确的。我试着预设Q,QB的值,但它似乎仍然不起作用
那么你能告诉我这个代码有什么问题吗 问题在于您的测试台。如果r和s都处于低激活状态,确保您的测试台只测试其中一个处于低激活状态 SR\u闩锁和的代码错误。 您没有将
s1
和r1
用于输出与非门n3
和n4
。
纠正的SR闩锁模块应为:
module SR_Latch_Nand(input S, R, C, output Q, QB);
wire s1, r1;
nand #8 n1(r1, R, C);
nand #8 n2(s1, S, C);
nand #8 n3(QB, s1, Q);
nand #8 n4(Q, r1, QB);
endmodule