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Verilog 循环中非阻塞语句前后的延迟有什么区别？_Verilog - Fatal编程技术网
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Verilog 循环中非阻塞语句前后的延迟有什么区别？

verilog

Verilog 循环中非阻塞语句前后的延迟有什么区别？,verilog,Verilog,这两段代码之间有什么区别 always @(posedge clk) begin r3 <= @(posedge clk) 1; r2 <= @(posedge clk) 1; ready = 0; while (r2 <= n) begin r2 <= @(posedge clk) r2 + 1; <--- never s

这两段代码之间有什么区别

    always @(posedge clk) begin
            r3 <= @(posedge clk) 1;
            r2 <= @(posedge clk) 1;
            ready = 0;
            while (r2 <= n) begin
                r2 <= @(posedge clk) r2 + 1;     <--- never stops executing
            end
    end


    always @(posedge clk) begin
            r3 <= @(posedge clk) 1;
            r2 <= @(posedge clk) 1;
            ready = 0;
            while (r2 <= n) begin
                @(posedge clk) r2 <= r2 + 1;     <--- normally executes
            end
    end

始终@（posedge clk）开始

r3当模拟器执行
r2时，应该注意的是，在代码中散布
@（posedge clk）
语句也不常见。@Marty，在我的代码中散布
@（posedge clk）
语句是一种不好的做法吗？@19293001：是的，尤其是对于需要合成的代码。事实上，我怀疑一个合成工具是否会看它！