Verilog 实现处理器(mips单周期)
我有一个小项目,在这个项目中,我需要通过Verilog实现一个MIPS单周期处理器。 在这里,我写的ALU和ALUControl和FileRegister,但我有一个问题,以实现Pc(程序计数器)为这个。。。我要这台电脑支持分机和跳转。 我需要支持分支机构的说明,但我不知道如何获得说明。 请帮我执行指令内存和Pc。 这是我的密码:Verilog 实现处理器(mips单周期),verilog,computer-architecture,mips32,Verilog,Computer Architecture,Mips32,我有一个小项目,在这个项目中,我需要通过Verilog实现一个MIPS单周期处理器。 在这里,我写的ALU和ALUControl和FileRegister,但我有一个问题,以实现Pc(程序计数器)为这个。。。我要这台电脑支持分机和跳转。 我需要支持分支机构的说明,但我不知道如何获得说明。 请帮我执行指令内存和Pc。 这是我的密码: module ALU(ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; outpu
module ALU(ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0
always @(ALUctl, A, B) begin //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1 : 0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0;
endcase
end
模块ALU(ALUctl、A、B、ALOUT、零);
输入[3:0]ALUctl;
输入[31:0]A,B;
输出寄存器[31:0]输出;
输出零;
分配零=(ALOUT==0)//如果ALOUT为0,则零为真
始终@(ALUctl,A,B)开始//重新评估这些更改
案例(ALUctl)
0:ALOUT这是pc的代码
module PC(clk , instruction , zero , branch , jump , pc );
input clk ;
input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;
wire[31:0] pcInc;
wire[31:0] Branch1 ;
wire[15:0] address;
wire[31:0] branchAdd;
reg[31:0] mux1;
wire select1 ;
wire[31:0] jumpAdd ;
output [31:0] pc ;
reg [31:0] pc ;
assign select1 = branch & zero ;
assign pcInc = pc + 4 ;
assign address = instruction[15:0];
assign Branch1 = {{16{address[15]}},address[15:0]} ; // sign extension
assign branchAdd = pcInc + ( branch << 2 ) ;
always@( branchAdd or pcInc or select1 )
begin
if ( select1 == 1 )
mux1 = branchAdd ;
else
mux1 = pcInc ;
end
assign jumpAdd = ( instruction[25:0] << 2 );
always@ ( jump or jumpAdd or mux1 )
begin
if ( jump == 1 )
npc = jumpAdd ;
else
npc = mux1;
end
always @(posedge clk )
pc <= npc;
模块PC(时钟、指令、零、分支、跳转、PC);
输入时钟;
输入[31:0]指令;
reg[31:0]npc;
输入零;
输入跳跃;
输入分支;
电线[31:0]pcInc;
导线[31:0]分支1;
电报[15:0]地址;
导线[31:0]分支;
reg[31:0]mux1;
导线选择1;
导线[31:0]跳线添加;
输出[31:0]pc;
注册[31:0]个人计算机;
分配select1=分支&零;
分配pcInc=pc+4;
分配地址=指令[15:0];
分配Branch1={{16{地址[15]},地址[15:0]};//符号分机
分配branchAdd=pcInc+(分支
端模
module ALUControl(ALUOp, FuncCode, ALUCtl);
input [1:0] ALUOp;
input [5:0] FuncCode;
output reg [3:0] ALUCtl;
always @(ALUOp, FuncCode) begin
if ( ALUOp == 2 )
case (FuncCode)
32: ALUCtl<=2; // add
34: ALUCtl<=6; //subtract
36: ALUCtl<=0; // and
37: ALUCtl<=1; // or
39: ALUCtl<=12; // nor
42: ALUCtl<=7; // slt
default: ALUCtl<=15; // should not happen
endcase
else
case (ALUOp)
0: ALUCtl<=2;
1: ALUCtl<=6;
default: ALUCtl<=15; // should not happen
endcase
end
module RegFile(ra1, rd1 , ra2 , rd2 , clk , RegWrite , wa ,wd );
input[4:0] ra1;
output[31:0] rd1;
input[4:0] ra2;
output[31:0] rd2;
input clk;
input werf ;
input[4:0] wa;
input[31:0] wd;
reg [31:0] registers[31:0];
assign rd1 = registers[ra1];
assign rd2 = registers[ra2];
always@ ( posedge clk )
if (RegWrite)
registers[wa] <= wd;
module pc( clock , pcin , pcout , reset );
input clock , reset;
input [31:0] pcin ;
output reg [31:0] pcout;
//initial begin pcout1=0; end
always @(posedge clock)
begin
if(reset)
pcout = 0 ;
else
pcout = pcin ;
end
module InsMem( clock,RD_Address,data_out );
input clock;
input [31:0] RD_Address;
output reg[31:0] data_out ;
reg [31:0] tmp;
reg [31:0]mem[16:0];
always@(posedge clock)
begin
data_out =mem[RD_Address];
end
endmodule您可能想看看stackexchange网站的提案:“可编程逻辑和FPGA设计”
module ALUControl(ALUOp, FuncCode, ALUCtl);
input [1:0] ALUOp;
input [5:0] FuncCode;
output reg [3:0] ALUCtl;
always @(ALUOp, FuncCode) begin
if ( ALUOp == 2 )
case (FuncCode)
32: ALUCtl<=2; // add
34: ALUCtl<=6; //subtract
36: ALUCtl<=0; // and
37: ALUCtl<=1; // or
39: ALUCtl<=12; // nor
42: ALUCtl<=7; // slt
default: ALUCtl<=15; // should not happen
endcase
else
case (ALUOp)
0: ALUCtl<=2;
1: ALUCtl<=6;
default: ALUCtl<=15; // should not happen
endcase
end
module RegFile(ra1, rd1 , ra2 , rd2 , clk , RegWrite , wa ,wd );
input[4:0] ra1;
output[31:0] rd1;
input[4:0] ra2;
output[31:0] rd2;
input clk;
input werf ;
input[4:0] wa;
input[31:0] wd;
reg [31:0] registers[31:0];
assign rd1 = registers[ra1];
assign rd2 = registers[ra2];
always@ ( posedge clk )
if (RegWrite)
registers[wa] <= wd;
module pc( clock , pcin , pcout , reset );
input clock , reset;
input [31:0] pcin ;
output reg [31:0] pcout;
//initial begin pcout1=0; end
always @(posedge clock)
begin
if(reset)
pcout = 0 ;
else
pcout = pcin ;
end
module InsMem( clock,RD_Address,data_out );
input clock;
input [31:0] RD_Address;
output reg[31:0] data_out ;
reg [31:0] tmp;
reg [31:0]mem[16:0];
always@(posedge clock)
begin
data_out =mem[RD_Address];
end