设计cpu，但价值不是'；t在verilog中移动 模块sram（地址、时钟、din、dout、we）//sram.v 参数addr_width=12，word_depth=110，word_width=16； 输入时钟，我们； 输入[addr_width-1:0]addr； 输入[word_width-1:0]din； 输出[word_width-1:0]dout； reg[word_width-1:0]mem[0:word_depth-1]； reg[word_width-1:0]dout； 始终@（posedge clk）开始 如果（！我们） mem[addr]

更改：

module sram(addr,clk,din,dout,we); //sram.v

parameter addr_width = 12, word_depth = 110, word_width = 16;

input clk,we;
input [addr_width-1:0] addr; 
input [word_width-1:0] din; 
output [word_width-1:0] dout; 

reg [word_width-1:0]mem[0:word_depth-1]; 
reg [word_width-1:0]dout;

always @ (posedge clk) begin
    if(!we)
        mem[addr] <= din[word_width-1:0]; 
    end
always @ (posedge clk) begin
    if(we)
        dout[word_width-1:0] <= mem[addr];
    end

endmodule



module cpu(clk,reset); //cpu.v

input clk, reset;


reg [15:0] dr, ac, ir;
reg [11:0] addr, pc;

reg [2:0] opcode;
reg [5:0]t;
reg we;
reg sc;

reg [15:0] din;
wire [15:0] dout;

sram sram(addr,clk,din,dout,we);

always @ (posedge clk or negedge reset) begin
    if(!reset) begin
        ir <= 16'd0; dr <= 16'd0; ac <= 16'd0; addr <= 12'd0; pc <= 12'd0; sc <= 0; t <= 0; we<=1;
        end

        else if(t==0) begin
        addr <= pc; sc<=1; 
        end

        else if(t==1) begin
        ir[15:0] <= dout[addr]; pc <= pc+1; 

        end

        else if(t==2) begin
        opcode <= ir[14:12]; 
        addr <= ir[11:0]; //no indirect mode, no i
        sc<=0;

        end

        else if(t==3) begin
            if(opcode==3'b111) begin
                ac <= 0; 

                end
            if(opcode==3'b000) begin
            end
        end

   end

always @ (negedge clk) begin
    if(!sc) begin
    t<=0;
    end
    else t<=t+1;
    end

endmodule


module tbcpu(); //tbcpu.v

reg clk,reset;

integer file_pointer;

cpu cpu(clk,reset);

always #5 clk = ~clk;

initial begin
    $readmemb("memory.dat", tbcpu.cpu.sram.mem); //assembly

    clk = 0; reset = 1; 
    #1 reset = 0;
    #1 reset = 1;

    #100 $finish;

    end
endmodule

ir[15:0]
    ir[15:0] <= dout[addr]; 

    ir[15:0] <= dout;