VHDL。为什么我的“rdy”值没有变为1？仍然困惑

在我的波形图中，我想知道为什么我的rdy值在400ns后没有变为1。 为什么我的d值在前两个输出之后没有输出任何东西？我已经试着找出错误好几个小时了，但是没有用。请帮忙，先谢谢你

这是我的波形图：

这是我的主要代码

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity GCD is
port(st , clk: in std_logic;        --clk temporarily taken out
     d1, d2 : in std_logic_vector(7 downto 0);
     dout : out std_logic_vector(7 downto 0);
     rdy : out std_logic);
end GCD;

architecture behav of GCD is
type state is (S0, S1, S2, S3, S4, S5, S6, S7);

--temporary clk
--signal clk : std_logic;

signal new_state : state;
signal eq : boolean;
signal eq1 : boolean;
signal lt : boolean;

begin
    --State transition
    process is
    variable curr_state : state:= S0;
    begin
        if clk = '1' then
        case curr_state is
            when S0 => 
                if st = '1' then curr_state := S1;
                end if;
            when S1 =>
                curr_state := S2;
            when S2 =>
                if eq and not lt then curr_state := S7;
                elsif lt and not eq then curr_state := S4;
                elsif not eq and not lt then curr_state := S3;
                end if;
            when S3 => 
                curr_state := S4;
            when S4 =>
                curr_state := S5;
           when S5 =>
                if eq1 = true then curr_state := S7;
                else curr_state := S6;
                end if;
            when S6 =>
                curr_state := S1;
            when S7 =>
                if st = '0' then curr_state := S0;
                end if;
        end case;
        new_state <= curr_state;
        end if;
        wait on clk;
    end process;


--Asserted Output Process
process is
variable M, N, dout_val, tmp: std_logic_vector(7 downto 0);
variable rdy_val : std_logic;
variable lt_val, eq_val, eq1_val : boolean;
begin
    rdy_val := '0';
    case new_state is

        when S0 =>
            M :=  d1;
            N := d2;
        when S1 =>
            if (to_integer(M) = to_integer(N)) then eq_val := true;
            elsif (to_integer(M) < to_integer(N)) then lt_val := true;
            end if;

        when S2 =>
        when S3 =>
            M := N;
            N := M;         
        when S4 =>
            if (to_integer(M) = 1) then eq1_val := true;
            end if;
        when S5 =>
        when S6 =>
            N := (N - M);
        when S7 =>
            rdy_val := '1';
            dout_val := M; 
    end case;
    dout <= dout_val;   
    rdy <= rdy_val;
    lt <= lt_val;
    eq <= eq_val;
    eq1 <= eq1_val;
    wait on new_state;
end process;
end behav;

这是我的测试台：

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

use work.all;

entity test_GCD is
end test_GCD;

architecture testbench of test_GCD is
signal m, n ,d: std_logic_vector(7 downto 0);
signal clk, st, rdy : std_logic;

begin

    --Component Instantiation
    device : GCD
    port map( clk => clk, st => st, d1 => m, 
              d2 => n, dout => d, rdy => rdy);


    --Process to Generate Test Data
    process is
    begin
        st <= '0';
        wait for 10ns;
        m <= "00001001";    --9 , 15    
        n <= "00001111";
        wait for 10ns;
        st <= '1';
        wait until rdy = '1';
        wait for 10ns;

        st <= '0';
        wait for 10ns;
        m <= "00001111";    --15, 9
        n <= "00001001";        
        wait for 10ns;
        st <= '1';
        wait until rdy = '1';
        wait for 10ns;

        st <= '0';
        wait for 10ns;      --15 , 14
        m <= "00001111";
        n <= "00001110";
        wait for 10ns;
        st <= '1';
        wait until rdy = '1';
        wait for 10ns;

        st <= '0';
        wait for 10ns;
        m <= "00010010";    --18 , 36
        n <= "00100100";
        wait for 30ns;
        st <= '1';
        wait until rdy = '1';
        wait for 10ns;

        st <= '0';
        wait for 10ns;
        m <= "01011011";    --91 = 01011011 , 39 = 00100111
        n <= "00100111";
        wait for 10ns;
        st <= '1';
        --wait for 10ns;
        wait until rdy = '1';
        wait for 10ns;

        st <= '0';
        wait for 10ns;
        m <= "01111111";    --127, 127
        n <= "01111111";
        wait for 10ns;
        st <= '1';
        wait until rdy = '1';
        wait for 10ns;

        wait;
    end process;

process is
begin
    clk <= '0', '1' after 15ns;
    wait for 30ns;
end process;

end testbench;

---

你是今天第二个带着同样作业在这里提问的人

在第三个st/rdy集合中，您打乱了计时关系：

    st <= '0';
    wait for 10ns;
    m <= "00010010";    --18 , 36
    n <= "00100100";
    wait for 30ns;
    st <= '1';
    wait until rdy = '1';
    wait for 10ns;

如果你看上面波形中的eq和lt，你会发现它们都是真的。这怎么可能？这里有一个过渡条件，你坚持S2

那么，这两个条件怎么能同时成立呢

    when S1 =>
        if (to_integer(M) = to_integer(N)) then 
            eq_val := true;
        elsif (to_integer(M) < to_integer(N)) then 
            lt_val := true;
        end if;

你开始得到正确的答案：

---

如果没有看到为您的项目提供的讲义，我希望您使用的是伪代码，如链接PDF的图1所示。它可能是在预期使用信号的情况下编写的。

出于好奇，您正在使用哪种VHDL工具，它不需要数字文字和单位之间的空格，例如10ns？另外，它不需要GCD的组件声明，您也没有synopsys软件包std_logic_unsigned或numeric_std_unsigned的use子句。我使用的是Capilano Computing的DesignWorks 5。您的DesignWorks在代码中演示的三种方式都不严格符合VHDL标准。谢谢您的回复。你能详细解释一下你说的“我错过了”是什么意思吗？谢谢你，大卫。我读了一遍，似乎解决了大部分问题。

    when S1 =>
        if (to_integer(M) = to_integer(N)) then 
            eq_val := true;
        elsif (to_integer(M) < to_integer(N)) then 
            lt_val := true;
        end if;

        when S3 =>
            tmp := M;
            M := N;
            N := tmp;