Vhdl Can'；t运行和银行测试台？
这是我的代码：Vhdl Can'；t运行和银行测试台？,vhdl,xilinx,Vhdl,Xilinx,这是我的代码： LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY AND_Bank_Test IS END AND_Bank_Test; ARCHITECTURE behavior OF AND_Bank_Test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT AND_Bank PORT( Input : IN std_logi
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY AND_Bank_Test IS
END AND_Bank_Test;
ARCHITECTURE behavior OF AND_Bank_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AND_Bank
PORT(
Input : IN std_logic_vector(7 downto 0);
AND_Bit : IN std_logic;
Output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Input : std_logic_vector(7 downto 0) := (others => '0');
signal AND_Bit : std_logic := '0';
--Outputs
signal Output : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AND_Bank PORT MAP (
Input => Input,
AND_Bit => AND_Bit,
Output => Output
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Input <= "00000001" ; AND_Bit <= 0;
wait for 100 ns;
Input <= "00111011" ; AND_Bit <= 1;
wait for 100 ns;
Input <= "10111011" ; AND_Bit <= 0;
wait for 100 ns;
Input <= "10110011" ; AND_Bit <= 1;
wait for 100 ns;
Input <= "01110111" ; AND_Bit <= 0;
wait for 100 ns;
Input <= "10110000" ; AND_Bit <= 1;
wait for 100 ns;
Input <= "11110011" ; AND_Bit <= 0;
wait for 100 ns;
Input <= "01110011" ; AND_Bit <= 1;
wait for 100 ns;
Input <= "10111111" ; AND_Bit <= 0;
wait for 100 ns;
Input <= "11111111" ; AND_Bit <= 1;
wait for 100 ns;
wait;
end process;
END;
--保持复位状态100纳秒
wait for 100 ns;
Input <= "0000000000000001" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000000111011" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000010111011" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000010110011" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000001110111" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000010110000" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000011110011" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000001110011" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000010111111" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000011111111" ; AND_Bit <= '1';
wait for 100 ns;
等待100ns；
输入您需要使用单个报价，例如：
Input <= "00000001" ; AND_Bit <= '0';
Input您需要使用单个报价，例如：
Input <= "00000001" ; AND_Bit <= '0';
Input关于您的错误，和_位
是标准逻辑。您必须写入和_位关于您的错误，和_位
是标准逻辑。您必须写入和_位我已更改为输入。您似乎已更改了输入/输出的宽度。当问题出现时，您是否仍有问题？你的要求变得模糊了。我已经改为输入了。你似乎已经改变了输入/输出的宽度。当问题出现时，您是否仍有问题？你所问的问题越来越模糊。我已改为输入，这意味着在你的程序中，映射端口的大小不匹配。您必须检查每个模块（和&测试台等）中的IN
和OUT
的大小。我已更改为输入，这意味着在您的程序中，映射端口的大小不匹配。您必须检查每个模块（和测试台等）中的输入和输出的大小。
wait for 100 ns;
Input <= "0000000000000001" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000000111011" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000010111011" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000010110011" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000001110111" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000010110000" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000011110011" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000001110011" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "0000000010111111" ; AND_Bit <= '0';
wait for 100 ns;
Input <= "0000000011111111" ; AND_Bit <= '1';
wait for 100 ns;
Input <= "00000001" ; AND_Bit <= '0';