Vhdl 第141行。分析错误,意外的标识符
伙计们,请帮我解决这个问题。在我的vhdl代码里是141行。解析错误,实现检查语法和模拟行为检查语法上的意外标识符是第141行:“K”附近的语法错误。 我的代码:Vhdl 第141行。分析错误,意外的标识符,vhdl,Vhdl,伙计们,请帮我解决这个问题。在我的vhdl代码里是141行。解析错误,实现检查语法和模拟行为检查语法上的意外标识符是第141行:“K”附近的语法错误。 我的代码: ——公司: --工程师: -- --创建日期:20:01:29 03/22/2016 --设计名称: --课程名称:反行为 --项目名称: --目标设备: --工具版本: --说明: -- --依赖项: -- --修订: --版本0.01-已创建文件 --补充意见: -- ------------------------------
——公司:
--工程师:
--
--创建日期:20:01:29 03/22/2016
--设计名称:
--课程名称:反行为
--项目名称:
--目标设备:
--工具版本:
--说明:
--
--依赖项:
--
--修订:
--版本0.01-已创建文件
--补充意见:
--
--------------------------------------------------------------
图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
--如果使用,请取消注释以下库声明
--具有有符号或无符号值的算术函数
--使用IEEE.NUMERIC_STD.ALL;
--如果正在实例化,请取消对以下库声明的注释
--此代码中的任何Xilinx原语。
--UNISIM图书馆;
--使用UNISIM.VComponents.all;
实体计数器为
端口(IN0:标准_逻辑中;
IN1:标准逻辑;
IN2:in标准逻辑;
IN3:in标准逻辑;
UDbar:标准逻辑中;
时钟:标准逻辑;
LDbar:标准逻辑中;
复位:在标准逻辑中;
Q:输出标准逻辑向量(3到0);
Qbar:输出标准逻辑向量(3到0);
EN:标准逻辑中);
末端计数器;
计数器的结构是
组件DFF是
端口(D:标准逻辑中的;
RST:标准逻辑中;
CLK:标准逻辑中;
Q:输出标准逻辑;
Qbar:输出标准逻辑);
端部元件;
组件MUX4x2为
端口(A:标准_逻辑中;
B:标准逻辑;
C:标准逻辑;
D:在标准逻辑中;
Sel0:标准逻辑中;
Sel1:标准逻辑中;
X:输出标准(U逻辑);
端部元件;
信号K、L、M、XS、Qmux、NQmux:std_逻辑_向量(3到0);
开始
MUX0:MUX4x2端口映射
(A=>Qmux(0),
B=>NQmux(0),
C=>IN0,
D=>IN0,
Sel0=>M(0),
Sel1=>非(LDbar),
X=>XS(0));
MUX1:MUX4x2端口映射
(A=>Qmux(1),
B=>NQmux(1),
C=>IN1,
D=>IN1,
Sel0=>M(1),
Sel1=>非(LDbar),
X=>XS(1));
MUX2:MUX4x2端口映射
(A=>Qmux(2),
B=>NQmux(2),
C=>IN2,
D=>IN2,
Sel0=>M(2),
Sel1=>不是LDbar,
X=>XS(2));
MUX3:MUX4x2端口映射
(A=>Qmux(3),
B=>NQmux(3),
C=>IN3,
D=>IN3,
Sel0=>M(3),
Sel1=>不是LDbar,
X=>XS(3));
D0:DFF端口映射
(D=>XS(0),
RST=>重置,
时钟=>时钟,
Q=>Qmux(0),
Qbar=>NQmux(0));
D1:DFF端口图
(D=>XS(1),
RST=>重置,
时钟=>时钟,
Q=>Qmux(1),
Qbar=>NQmux(1));
D2:DFF端口图
(D=>XS(2),
RST=>重置,
时钟=>时钟,
Q=>Qmux(2),
Qbar=>NQmux(2));
D3:DFF端口映射
(D=>XS(3),
RST=>重置,
时钟=>时钟,
Q=>Qmux(3),
Qbar=>NQmux(3));
进程(K、L、Qmux、重置、时钟、LDbar、UDbar、EN)
K(0)在进程(K,L,…)
行之后缺少begin
语句
在显示错误的行之前查看行是很常见的。错误消息中的行号并不总是您出错的那一行。我教VHDL。缺少begin
似乎是一个常见的错误。VHDL中的许多结构具有类似的三行结构
<something>
-- declare stuff here
begin
-- do stuff here
end <something>;
及
及
及
Matthew Taylor和jeff都没有给您留下一个有效的设计,因为还有更多的语法错误
除了他们的begin
之外,我对流程做了一些更改:
process ( k, l, qmux, nqmux, udbar, en) -- reset, clock, ldbar, udbar, en )
begin -- added per scary_jeff, matthew taylor
-- k(0) <= udbar and en; ---!!!!this line!!!!!-----
-- l(0) <= not udbar and en;
-- m(0) <= k(0) or l(0);
-- m(0) <= en; -- inverts qmux(0) for up or down
k(1) <= en and qmux(0) and udbar;
l(1) <= en and nqmux(0) and not udbar; -- nqmux not qmux
m(1) <= k(1) or l(1);
-- m(1) <= en and (
-- ( qmux(0) and udbar) or
-- ( nqmux(0) and not udbar)
-- );
k(2) <= en and qmux(0) and qmux(1) and udbar;
l(2) <= en and nqmux(0) and nqmux(1) and not udbar; -- nqmux not qmux
m(2) <= k(2) or l(2);
k(3) <= en and qmux(0) and qmux(1) and qmux(2) and udbar;
l(3) <= en and nqmux(0) and nqmux(1) and nqmux(2) and not udbar; -- nqmux
m(3) <= k(3) or l(3);
-- in3 = '0'; -- These are input ports and signals ( use "<=" )
-- in2 = '0';
-- in1 = '1';
-- in0 = '1';
-- wait until clock'event and clock = '1'; -- none of this is used
-- if reset = '1' and ldbar = '1' and en = '0' then
-- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '0' and qmux(3)= '0';
-- elsif reset='1' and ldbar='0' and en='0' then
-- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '0' and qmux(3)= '0';
--
-- elsif reset='0' and ldbar='0' and en = '0' then
-- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '1' and qmux(3)= '1';
--
-- end if;
end process;
q <= qmux; -- added
qbar <= nqmux; -- added
end architecture behavioral;
我还将a、b和c、d输入交换到多路复用器,以使用ldbar作为sel1。有一个要求,实际表达式必须是静态表达式
这些变化以及假设正复位的升级测试台、mux4x2和dff给出:
正在工作的上下计数器
因此,设计是99%在那里。除了进程开始之外的错误是没有获得正确的增量和减量值,无法在qmux(n)和nqmux(n)之间切换,并且进程中出现了一些错误
哦,请注意计数器中进程下方添加的两个并发信号分配,分别将qmux分配给q和nqmux分配给qbar
我会做一些不同的事情,没有中间信号来表示m(3到1),in0-in1可能是inp(3到0)
试验台:
library ieee;
use ieee.std_logic_1164.all;
entity counter_ud_tb is
end entity;
architecture foo of counter_ud_tb is
signal in0: std_logic := '1'; -- load value "1111"
signal in1: std_logic := '1';
signal in2: std_logic := '1';
signal in3: std_logic := '1';
signal udbar: std_logic;
signal clock: std_logic := '0';
signal ldbar: std_logic;
signal reset: std_logic;
signal q: std_logic_vector (3 downto 0);
signal qbar: std_logic_vector (3 downto 0);
signal en: std_logic;
begin
DUT:
entity work.counter
port map (
in0 => in0,
in1 => in1,
in2 => in2,
in3 => in3,
udbar => udbar,
clock => clock,
ldbar => ldbar,
reset => reset,
q => q,
qbar => qbar,
en => en
);
CLKGEN:
process
begin
wait for 5 ns;
clock <= not clock;
if now > 380 ns then
wait;
end if;
end process;
STIMULI:
process
begin
wait for 6 ns;
reset <= '1';
ldbar <= '1';
en <= '0';
udbar <= '1'; -- up
wait for 20 ns;
reset <= '0';
ldbar <= '0';
wait for 10 ns;
ldbar <= '1';
wait for 10 ns;
en <= '1';
wait for 160 ns;
udbar <= '0'; -- down
wait for 160 ns;
en <= '0';
wait;
end process;
end architecture;
ieee库;
使用ieee.std_logic_1164.all;
实体计数器是
终端实体;
计数器的体系结构foo是
0中的信号:标准逻辑:='1';--负载值“1111”
信号in1:std_逻辑:='1';
信号in2:std_逻辑:='1';
信号输入3:std_逻辑:='1';
信号udbar:std_逻辑;
信号时钟:标准逻辑:='0';
信号ldbar:标准逻辑;
信号复位:标准逻辑;
信号q:std_逻辑_向量(3到0);
信号qbar:std_逻辑_向量(3到0);
信号en:std_逻辑;
开始
DUT:
实体工作台
港口地图(
in0=>in0,
in1=>in1,
in2=>in2,
in3=>in3,
udbar=>udbar,
时钟=>时钟,
ldbar=>ldbar,
重置=>重置,
q=>q,
qbar=>qbar,
en=>en
);
克莱根:
过程
开始
等待5ns;
时钟380纳秒
等待
如果结束;
结束过程;
刺激:
过程
开始
等待6ns;
以相同方式重置您列出的函数
两次。请删除与语法错误无关的所有代码。
architecture
-- declare stuff here (eg constant, variable declarations)
begin
-- concurrent code here
end architecture;
function
-- declare stuff here (eg constant, variable declarations)
begin
-- sequential code here
end function;
procedure
-- declare stuff here
begin
-- sequential code here
end procedure;
process ( k, l, qmux, nqmux, udbar, en) -- reset, clock, ldbar, udbar, en )
begin -- added per scary_jeff, matthew taylor
-- k(0) <= udbar and en; ---!!!!this line!!!!!-----
-- l(0) <= not udbar and en;
-- m(0) <= k(0) or l(0);
-- m(0) <= en; -- inverts qmux(0) for up or down
k(1) <= en and qmux(0) and udbar;
l(1) <= en and nqmux(0) and not udbar; -- nqmux not qmux
m(1) <= k(1) or l(1);
-- m(1) <= en and (
-- ( qmux(0) and udbar) or
-- ( nqmux(0) and not udbar)
-- );
k(2) <= en and qmux(0) and qmux(1) and udbar;
l(2) <= en and nqmux(0) and nqmux(1) and not udbar; -- nqmux not qmux
m(2) <= k(2) or l(2);
k(3) <= en and qmux(0) and qmux(1) and qmux(2) and udbar;
l(3) <= en and nqmux(0) and nqmux(1) and nqmux(2) and not udbar; -- nqmux
m(3) <= k(3) or l(3);
-- in3 = '0'; -- These are input ports and signals ( use "<=" )
-- in2 = '0';
-- in1 = '1';
-- in0 = '1';
-- wait until clock'event and clock = '1'; -- none of this is used
-- if reset = '1' and ldbar = '1' and en = '0' then
-- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '0' and qmux(3)= '0';
-- elsif reset='1' and ldbar='0' and en='0' then
-- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '0' and qmux(3)= '0';
--
-- elsif reset='0' and ldbar='0' and en = '0' then
-- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '1' and qmux(3)= '1';
--
-- end if;
end process;
q <= qmux; -- added
qbar <= nqmux; -- added
end architecture behavioral;
signal k, l, m: std_Logic_vector (3 downto 1);
signal xs, qmux, nqmux: std_logic_vector (3 downto 0);
mux0: -- swap inputs to use ldbar directly
mux4x2
port map (
a => in0, -- was qmux(0),
b => in0, -- was nqmux(0),
c => qmux(0), -- was in0,
d => nqmux(0), -- was in0,
sel0 => en, -- was m(0), -- an optimization
sel1 => ldbar, -- was not ldbar
x => xs(0)
);
mux1:
mux4x2
port map (
a => in1, -- was qmux(1),
b => in1, -- was nqmux(1),
c => qmux(1), -- was in1,
d => nqmux(1), -- was in1,
sel0 => m(1),
sel1 => ldbar, -- was not ldbar
x => xs(1)
);
mux2:
mux4x2
port map (
a => in2, -- was qmux(2),
b => in2, -- was nqmux(2),
c => qmux(2), -- was in2,
d => nqmux(2), -- was in2,
sel0 => m(2),
sel1 => ldbar, -- was not ldbar
x => xs(2)
);
mux3:
mux4x2
port map (
a => in3, -- was qmux(3),
b => in3, -- was nqmux(3),
c => qmux(3), -- was in3,
d => nqmux(3), -- was in3,
sel0 => m(3),
sel1 => ldbar, -- was not ldbar
x => xs(3)
);
library ieee;
use ieee.std_logic_1164.all;
entity counter_ud_tb is
end entity;
architecture foo of counter_ud_tb is
signal in0: std_logic := '1'; -- load value "1111"
signal in1: std_logic := '1';
signal in2: std_logic := '1';
signal in3: std_logic := '1';
signal udbar: std_logic;
signal clock: std_logic := '0';
signal ldbar: std_logic;
signal reset: std_logic;
signal q: std_logic_vector (3 downto 0);
signal qbar: std_logic_vector (3 downto 0);
signal en: std_logic;
begin
DUT:
entity work.counter
port map (
in0 => in0,
in1 => in1,
in2 => in2,
in3 => in3,
udbar => udbar,
clock => clock,
ldbar => ldbar,
reset => reset,
q => q,
qbar => qbar,
en => en
);
CLKGEN:
process
begin
wait for 5 ns;
clock <= not clock;
if now > 380 ns then
wait;
end if;
end process;
STIMULI:
process
begin
wait for 6 ns;
reset <= '1';
ldbar <= '1';
en <= '0';
udbar <= '1'; -- up
wait for 20 ns;
reset <= '0';
ldbar <= '0';
wait for 10 ns;
ldbar <= '1';
wait for 10 ns;
en <= '1';
wait for 160 ns;
udbar <= '0'; -- down
wait for 160 ns;
en <= '0';
wait;
end process;
end architecture;