VHDL:std_逻辑_向量左移位和右移位运算符？

在标准逻辑向量上，VHDL中如何形成右移或左移

它不会工作，为什么`

AN <= "0001";        
CounterProcess: process(CLK,Switch)
    begin
    if rising_edge(CLK) then
        if prescaler < limit then 
            prescaler <= prescaler + 1;
            else
                prescaler <= (others => '0'); 
                counter <= counter + 1;
                AN sll 1;
        end if;
    end if; 
    end process;
    An <= anode;

    Segment <= counter; 

    end Behavioral;

难道不包括执行左移操作所需的工具吗

---

完整代码

entity Main is
PORT(
        CLK: in std_logic;
        LED: out std_logic_vector (7 downto 0);
        Switch: in std_logic_vector(7 downto 0);
        Segment: out std_logic_vector (7 downto 0); 
        AN: out std_logic_vector (3 downto 0) 
        );

end Main;


architecture Behavioral of Main is
signal counter: std_logic_vector (7 downto 0);
signal prescaler:  std_logic_vector(25 downto 0);
signal limit: std_logic_vector (25 downto 0);
signal anode: std_logic_vector (3 downto 0);
begin
AN <= "0001";

ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz; 
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <=      "00000000000000000000000001"; -- 50 MHz
end case;
end process;


CounterProcess: process(CLK,Switch)
begin
if rising_edge(CLK) then
    if prescaler < limit then 
        prescaler <= prescaler + 1;
        else
            prescaler <= (others => '0'); 
            counter <= counter + 1;
            AN sll AN 1;
    end if;
end if; 
end process;

Segment <= counter; 

end Behavioral;

实体主体是
港口(
CLK：标准逻辑中；
LED：输出标准逻辑向量（7到0）；
开关：标准逻辑向量（7到0）；
段：输出标准逻辑向量（7到0）；
AN:out标准逻辑向量（3到0）
);
端干管；
主要信息系统的架构
信号计数器：标准逻辑向量（7到0）；
信号预分频器：标准逻辑向量（25到0）；
信号限值：标准逻辑矢量（25至0）；
信号阳极：标准逻辑向量（3到0）；
开始
限制编辑1:

使用重置逻辑编辑的代码，请注意端口列表中添加了reset信号，删除了该值的异步行设置，将reset添加到反过程的灵敏度列表中，添加了if（reset='1'）行，将
if
更改为
elsif
，并更改换档线：

我实际上不知道你的
An除了trumpetlicks所说的之外，还可以使用这些包。确保启用VHDL-2008开关。另外，请先与您的FPGA供应商联系，因为这些需要VHDL-2008更新：

library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use ieee.numeric_std.all;
   use ieee.numeric_std_unsigned.all;

以上软件包均为IEEE标准。包
STD\u LOGIC\u ARITH
和
STD\u LOGIC\u unsigned
不是IEEE标准。还要注意的是，
numeric\u std
和
std\u LOGIC\u ARITH
相互冲突，使得使用类型
signed
和
unsigned
非常困难（远远超出了基本用法）。请注意，
std\u logic\u unsigned
与
numeric\u std\u unsigned
冲突。因此，如果您的合成工具支持
数值\u std\u unsigned
，我建议改用它。此外，如果没有，您应该提交一份错误报告。
请查看我的修订版-新错误消息：解析错误、意外SLL、预期OPENPAR或勾选或LSQBRACK@BobBurt-另一个问题是，实际上有两个电路驱动同一个寄存器“AN”。在代码顶部，您有一个“是”。。你说得完全正确。但问题是，我无法在开始之前设置值，因为在我的实体中设置了。@BobBurt传统上这是通过重置逻辑完成的，我将尝试在我的答案中发布上面的示例。我不知道重置按钮如何工作？？什么会触发？。。我无法访问FPGA上的重置按钮，访问它会很奇怪。。我收到这个错误消息：解析错误，意外的SLL，期望OPENPAR或TICK或LSQBRACK
entity Main is PORT(
    RESET:   in  std_logic;
    CLK:     in  std_logic;
    LED:     out std_logic_vector(7 downto 0);
    Switch:  in  std_logic_vector(7 downto 0);
    Segment: out std_logic_vector(7 downto 0); 
    AN:      out std_logic_vector(3 downto 0)
);
end Main;

architecture Behavioral of Main is
signal counter:   std_logic_vector(7  downto 0);
signal prescaler: std_logic_vector(25 downto 0);
signal limit:     std_logic_vector(25 downto 0);
signal anode:     std_logic_vector(3  downto 0);

begin

ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz; 
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <=     "00000000000000000000000001"; -- 50 MHz
end case;
end process;


CounterProcess: process(RESET, CLK, Switch)
begin
    if(RESET = '1') then
        AN <= "0001";
    elsif rising_edge(CLK) then
        if prescaler < limit then 
            prescaler <= prescaler + 1;
        else
            prescaler <= (others => '0'); 
            counter <= counter + 1;
            AN <= std_logic_vector(unsigned(AN) sll 1);
        end if;
    end if;
end process;

An <= anode;
Segment <= counter; 

end Behavioral;

AN sll 1;

AN <= AN sll 1;

counter <= counter + 1;

library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use ieee.numeric_std.all;
   use ieee.numeric_std_unsigned.all;