Components 多VHDL组件实例化
以下一般性问题: 如何使用三个子模块(SubX、SubY、SubZ)设置以下系统(主): 代码如下:Components 多VHDL组件实例化,components,vhdl,instantiation,Components,Vhdl,Instantiation,以下一般性问题: 如何使用三个子模块(SubX、SubY、SubZ)设置以下系统(主): 代码如下: entity System is port ( clk_clk : in std_logic; pwm : OUT std_logic ); end entity System_Misc; architecture rtl of System is comp
entity System is
port (
clk_clk : in std_logic;
pwm : OUT std_logic
);
end entity System_Misc;
architecture rtl of System is
component SubX
port(clk : IN STD_LOGIC;
pwmSubX : OUT STD_LOGIC;
end component SubX;
component SubZ
port(clk : IN STD_LOGIC;
pwmSubZ : OUT STD_LOGIC;
end component SubZ;
begin
component SubX
port map(
clk => clk_clk,
pwmSubX => pwm
);
component SubZ
port map(
clk => clk_clk,
pwmSubZ => pwm
);
end architecture rtl;
这种方法正确吗?因为SubZ在Main和SubX中都进行了实例化(此处未显示)。如果这样做,我会得到一个错误,即无法将pwmSubX和pwmSubZ连接到同一输出pwm(主)。
解决此问题的正确方法是什么和/或您将如何实施
谢谢 端口有多个驱动器
pwm
您需要为每个部件使用不同的信号,并指定SubX
和SubZ
的输出将如何生成pwm
输出
如果SubX
或SubZ
是在其他地方实例化的,则没有区别
architecture rtl of System is
component SubX
port(clk : IN STD_LOGIC;
pwmSubX : OUT STD_LOGIC;
end component SubX;
component SubZ
port(clk : IN STD_LOGIC;
pwmSubZ : OUT STD_LOGIC;
end component SubZ;
signal pwmSubX : std_logic;
signal pwmSubZ : std_logic;
begin
component SubX
port map(
clk => clk_clk,
pwmSubX => pwmSubX
);
component SubZ
port map(
clk => clk_clk,
pwmSubZ => pwmSubZ
);
-- Do what you need with both pwmSubX and pwmSubZ in order to assign
-- the pwm port
pwm <= pwmSubX or pwmSubZ;
end architecture rtl;
系统的体系结构rtl是
组件子X
端口(时钟:在标准逻辑中;
pwmSubX:输出标准_逻辑;
端部分量SubX;
分量子z
端口(时钟:在标准逻辑中;
pwmSubZ:输出标准_逻辑;
端部组件SubZ;
信号pwmSubX:std_逻辑;
信号pwmSubZ:std_逻辑;
开始
组件子X
港口地图(
clk=>clk_clk,
pwmSubX=>pwmSubX
);
分量子z
港口地图(
clk=>clk_clk,
pwmSubZ=>pwmSubZ
);
--使用pwmSubX和pwmSubZ执行您需要的操作,以便分配
--pwm端口
pwm每个组件实例化都被细化为两个嵌套的块语句和零个或多个过程语句以及更多的块语句
每个过程中分配的每个信号都有一个驱动器
类型std_逻辑是一个已解析的std_逻辑。解析意味着一个或多个驱动器值被解析为信号的有效值
充实(并纠正)你的例子:
library ieee; -- added subx entity/architecture
use ieee.std_logic_1164.all;
entity subx is
port (
clk: in std_logic;
pwmsubx: out std_logic
);
end entity;
architecture foo of subx is
signal pwm: std_logic;
component subz is
port (
clk: in std_logic;
pwmsubz: out std_logic
);
end component;
signal pwmsubz: std_logic;
begin
SUB_Z:
subz
port map (
clk => clk,
pwmsubz => pwmsubz
);
pwm <= pwmsubz after 2 us;
pwmsubx <= pwm;
end architecture;
library ieee; -- added subz entity/architecture
use ieee.std_logic_1164.all;
entity subz is
port (
clk: in std_logic;
pwmsubz: out std_logic
);
end entity;
architecture foo of subz is
signal pwm: std_logic;
begin
pwm <= clk after 1 us;
pwmsubz <= pwm;
end architecture;
library ieee; -- added context clause
use ieee.std_logic_1164.all;
entity system is
port (
clk_clk: in std_logic;
pwm: out std_logic
);
end entity; -- system_misc;
architecture rtl of system is
component subx
port(clk: in std_logic;
pwmsubx: out std_logic -- ;
); -- added
end component subx;
component subz
port(clk: in std_logic;
pwmsubz: out std_logic -- ;
); -- added
end component subz;
begin
U0: -- added label
component subx
port map (
clk => clk_clk,
pwmsubx => pwm
);
U1: -- added label
component subz
port map (
clk => clk_clk,
pwmsubz => pwm
);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity system_tb is
end entity;
architecture foo of system_tb is
signal clk: std_logic := '0';
signal pwm: std_logic;
begin
DUT:
entity work.system
port map (
clk_clk => clk,
pwm => pwm
);
STIMULUS:
process
begin
wait for 3 us;
clk <= not clk;
if now > 15 us then
wait;
end if;
end process;
end architecture;
library ieee;--添加了subx实体/体系结构
使用ieee.std_logic_1164.all;
实体subx是
港口(
clk:标准逻辑中;
pwmsubx:输出标准_逻辑
);
终端实体;
subx的架构foo是
信号pwm:std_逻辑;
组件subz是
港口(
clk:标准逻辑中;
pwmsubz:输出标准_逻辑
);
端部元件;
信号pwmsubz:std_逻辑;
开始
副主席:
苏伯兹
港口地图(
时钟=>clk,
pwmsubz=>pwmsubz
);
脉宽调制
);
终端架构rtl;
图书馆ieee;
使用ieee.std_logic_1164.all;
实体系统是
终端实体;
系统的体系结构foo_tb是
信号时钟:标准逻辑:='0';
信号pwm:std_逻辑;
开始
DUT:
实体工作系统
港口地图(
clk_clk=>clk,
pwm=>pwm
);
刺激:
过程
开始
等我们三个;
那么clk 15美国
等待
如果结束;
结束过程;
终端架构;
请注意,两个组件subx和subz在分配到其输出之前具有内部信号,这些输出与系统中的pwm相关
这使我们可以在波形上看到一些东西,以演示分辨率的影响:
当两个驱动程序发生冲突时,我们得到“X”(红色)
合成软件通常对将两个驱动程序短接在一起持模糊看法,通常不允许有线或有线和内部连接。您得到的任何错误都可能来自合成工具,而不是VHDL投诉(您可以看到它模拟得很好)
如何解决同一信号的两个驱动器的问题取决于信号的含义,这在您的示例中并不明显。正如AndréSouto所指出的,您可以使用逻辑设备将两个输出选通在一起。当您将两个不同的输出连接到同一pwm
端口时,您希望发生什么?感谢经验拉纳多!
library ieee; -- added subx entity/architecture
use ieee.std_logic_1164.all;
entity subx is
port (
clk: in std_logic;
pwmsubx: out std_logic
);
end entity;
architecture foo of subx is
signal pwm: std_logic;
component subz is
port (
clk: in std_logic;
pwmsubz: out std_logic
);
end component;
signal pwmsubz: std_logic;
begin
SUB_Z:
subz
port map (
clk => clk,
pwmsubz => pwmsubz
);
pwm <= pwmsubz after 2 us;
pwmsubx <= pwm;
end architecture;
library ieee; -- added subz entity/architecture
use ieee.std_logic_1164.all;
entity subz is
port (
clk: in std_logic;
pwmsubz: out std_logic
);
end entity;
architecture foo of subz is
signal pwm: std_logic;
begin
pwm <= clk after 1 us;
pwmsubz <= pwm;
end architecture;
library ieee; -- added context clause
use ieee.std_logic_1164.all;
entity system is
port (
clk_clk: in std_logic;
pwm: out std_logic
);
end entity; -- system_misc;
architecture rtl of system is
component subx
port(clk: in std_logic;
pwmsubx: out std_logic -- ;
); -- added
end component subx;
component subz
port(clk: in std_logic;
pwmsubz: out std_logic -- ;
); -- added
end component subz;
begin
U0: -- added label
component subx
port map (
clk => clk_clk,
pwmsubx => pwm
);
U1: -- added label
component subz
port map (
clk => clk_clk,
pwmsubz => pwm
);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity system_tb is
end entity;
architecture foo of system_tb is
signal clk: std_logic := '0';
signal pwm: std_logic;
begin
DUT:
entity work.system
port map (
clk_clk => clk,
pwm => pwm
);
STIMULUS:
process
begin
wait for 3 us;
clk <= not clk;
if now > 15 us then
wait;
end if;
end process;
end architecture;