Keyboard FF/闩锁和其他警告

Keyboard FF/闩锁和其他警告,keyboard,vhdl,Keyboard,Vhdl,有人能帮我找出我的VHDL代码有什么问题吗?代码如下: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity main is port( --50MHz clock cp : in std_logic; --reset signal reset : in

有人能帮我找出我的VHDL代码有什么问题吗?代码如下:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        --50MHz clock
        cp : in std_logic;
        --reset signal
        reset : in std_logic;
        --PS/2 data and clock lines
        ps2d, ps2c : in std_logic;
        --7-segment display segments
        segments : out std_logic_vector (7 downto 0);
        --anode control
        an : out std_logic_vector (3 downto 0);
        --data out to LEDs
        dout : out std_logic_vector (7 downto 0)
    );
end main;

architecture Behavioral of main is
    --data from keyboard entity (scancode)
    signal data : std_logic_vector (7 downto 0);
    --7 segments of display
    signal segReg, segNext : std_logic_vector (6 downto 0);
    signal tickDone : std_logic;
begin
    --just entity that reads PS/2 keyboard data
    --rx_done is tick (20 ns)
    S1: entity keyboard port map ( cp => cp, ps2d => ps2d, ps2c => ps2c,
                          rx_done => tickDone, dout => data);
    dout <= data;
    an <= "1110";
    segments(6 downto 0) <= segReg;
    --turn off dot
    segments(7) <= '1';
    process (cp, reset)
    begin
        if reset = '1' then
            segReg <= (others => '0');
        elsif rising_edge (cp) then
            segReg <= segNext;
        end if;
    end process;

    process (tickDone, segReg)
    begin
        segNext <= segReg;
        if tickDone = '1' then
            if data = x"16" then
                --number 1
                segNext <= "1001111";
            elsif data = x"1E" then
                --number 2
                segNext <= "0010010";
            elsif data = x"26" then
                --number 3
                segNext <= "0000110";
            elsif data = x"25" then
                --number 4
                segNext <= "1001100";
            else
                segNext <= "1111111";
            end if;
        end if;
    end process;

end Behavioral;
当我尝试合成它/生成编程文件时,会收到以下警告:

WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:1710 - FF/Latch  <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1710 - FF/Latch  <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <reset_IBUF> is incomplete. The signal
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_6> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
有人能帮我吗?我一直在看代码,没有发现任何错误,但很明显我做错了什么

1工艺灵敏度列表中缺少以下信号这可能是Xilinx ISE缺陷吗?我不明白为什么我需要第48行的过程灵敏度列表中的任何其他信号

2由于其他FF/闩锁修剪,块中的常量值为0 OK,我做错了什么?我根本不想使用闩锁

3信号复位_IBUF无负载。PAR将不会尝试路由此信号。这是什么意思?我的重置信号有什么问题?为什么它不完整

这段代码是我尝试将PS/2键盘与Spartan 3启动板结合使用的代码。实体键盘进行读取,当我单独测试时,它工作正常,我在LED上看到的dout信号上得到正确的扫描代码。rx_done是勾选20ns,表示扫描码已成功读取

所以我只是想看看在我的第二个过程中,我是否能识别出扫描代码。我正在比较数据信号,将正确的值放入SEGNEX信号,并在7段显示器上显示一些东西。当我让它工作时,我将实现正确的行为检测所有扫描代码,用于额外的按键以及按键下降和按键上升事件

我不确定是否需要描述其他内容,如果需要,请给我留言:

谢谢你的帮助

编辑:编辑的代码将数据添加到敏感度列表,否则添加到if子句:

不幸的是,在这些编辑之后,我仍然有以下警告:

WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:1710 - FF/Latch  <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1710 - FF/Latch  <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <reset_IBUF> is incomplete. The signal
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_6> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

您的第二个进程似乎试图将tickDone用作时钟信号,但您没有适当地使用它,即:如果是rising_EdgicKDone或类似的,那么如果tickDone='1',则创建锁存而不是触发器。对于锁存器,虽然tickDone为高,但输出取决于不在灵敏度列表中的数据信号的状态。最后,使用敏感度列表中的segReg,即代码的编写方式,将segReg异步分配给segNext


您是否忘记了将第二个进程中的所有内容封装在使用cp信号作为时钟的if语句中?您所写的内容将更有意义…

在您的组合过程中,您正在读取tickDone、segReg和数据。敏感度列表中缺少后者,这会导致锁定

另外,不要使用STD_LOGIC_ARITH或STD_LOGIC_UNSIGNED。它们没有标准化,并且存在一些问题

2由于其他FF/闩锁修剪,在块OK中具有恒定值0, 我做错了什么?我根本不想使用闩锁


这说明这些存储元素是由常量驱动的,而不是它们是锁存器。你模拟过吗?

滴答声不是时钟信号。它只是一个时钟宽度的信号,告诉我何时可以安全地从键盘实体读取数据。如果rising_edgecp确实消除了错误,则将所有内容都包装起来,但它根本不起作用。。。我在一些书中发现了这种方法,我认为它会起作用。。。他们使用了相同的两个过程,一个是DO Reg。如果设置了正确的灵敏度列表,您是否可以更新警告消息?您仍然有一个闩锁,因为在if tickDone='1'子句上没有else。我已经编辑了我的问题,在将数据添加到敏感度列表和将其他数据添加到if子句之后,我仍然存在问题!!!!在模拟之后,我意识到tickDone从未被驱动到“1”。检查完键盘实体后,我注意到我在FSM中输入了错别字,我跳过了tickDone被驱动到“1”的最终状态。。。再次感谢: