Keyboard PS2键盘延迟错误/VHDL

我有一个问题是由这个键盘接口引起的。我正在尝试制作一架带有键盘和扩音器的数字钢琴，但当我们按下按钮时，声音就不出来了；延迟约1秒。你能帮我解决这个问题吗？同样，当我们更改代码部分时

---

Shift2\u next您必须将设计更改为同步，特别是在使用PS2时。我建议您检查PS2的时钟，确保它连接到25 MHz引脚，或者尝试使用更高频率的时钟并将其分割，直到获得正确的计时。附上一个时钟除以3的例子，你可以改变它并使用它

致以最良好的祝愿

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

entity divide_by_3 is
    port (
        cout   :out std_logic;  -- Output clock
        clk    :in  std_logic;  -- Input clock
        reset  :in  std_logic   -- Input reset
    );
end entity;

architecture rtl of divide_by_3 is
    signal pos_cnt :std_logic_vector (1 downto 0);
    signal neg_cnt :std_logic_vector (1 downto 0);
begin
    process (clk, reset) begin
        if (reset = '1') then
            pos_cnt <= (others=>'0');
        elsif (rising_edge(clk)) then
            if (pos_cnt = 2) then
                pos_cnt <= pos_cnt + 1;
            end if;
        end if;
    end process;

    process (clk, reset) begin
        if (reset = '1') then
            neg_cnt <= (others=>'0');
        elsif (falling_edge(clk)) then
            if (neg_cnt = 2) then
                neg_cnt <= neg_cnt + 1;
            end if;
        end if;
    end process;

    cout <= '1' when ((pos_cnt /= 2) and (neg_cnt /= 2)) else
            '0';
end architecture;
-------------------------------------------------------
--  Testbench to check the divide_by_3 logic
-------------------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_textio.all;
    use std.textio.all;

entity div3_tb is
end entity;
architecture test of div3_tb is

    signal cout   :std_logic;
    signal clk    :std_logic := '1';
    signal reset  :std_logic := '1';

    component divide_by_3 is
    port (
        cout   :out std_logic;
        clk    :in  std_logic;
        reset  :in  std_logic
    );
    end component;
begin

    -- Generate clock
    clk   <= not clk after 10 ns;
    reset <= '0' after 20 ns;

    Inst_div3 : divide_by_3


      port map (
            cout   => cout,   -- Output
            clk    => clk,    -- Input
            reset  => reset   -- Iinput
        );
    end architecture

;

---

这种设计没有双FF输入同步，这对于PS2协议至关重要。它不是一个同步设计，因为shift1和shift2是通过一个自生时钟信号来计时的->使用能够改进这一部分。为什么在ps2c和ps2d上使用AND过滤器？您可以假定这些导线没有故障。您的电路不注意：总线空闲、启动条件、奇偶校验、总线上的结束条件。

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

entity divide_by_3 is
    port (
        cout   :out std_logic;  -- Output clock
        clk    :in  std_logic;  -- Input clock
        reset  :in  std_logic   -- Input reset
    );
end entity;

architecture rtl of divide_by_3 is
    signal pos_cnt :std_logic_vector (1 downto 0);
    signal neg_cnt :std_logic_vector (1 downto 0);
begin
    process (clk, reset) begin
        if (reset = '1') then
            pos_cnt <= (others=>'0');
        elsif (rising_edge(clk)) then
            if (pos_cnt = 2) then
                pos_cnt <= pos_cnt + 1;
            end if;
        end if;
    end process;

    process (clk, reset) begin
        if (reset = '1') then
            neg_cnt <= (others=>'0');
        elsif (falling_edge(clk)) then
            if (neg_cnt = 2) then
                neg_cnt <= neg_cnt + 1;
            end if;
        end if;
    end process;

    cout <= '1' when ((pos_cnt /= 2) and (neg_cnt /= 2)) else
            '0';
end architecture;
-------------------------------------------------------
--  Testbench to check the divide_by_3 logic
-------------------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_textio.all;
    use std.textio.all;

entity div3_tb is
end entity;
architecture test of div3_tb is

    signal cout   :std_logic;
    signal clk    :std_logic := '1';
    signal reset  :std_logic := '1';

    component divide_by_3 is
    port (
        cout   :out std_logic;
        clk    :in  std_logic;
        reset  :in  std_logic
    );
    end component;
begin

    -- Generate clock
    clk   <= not clk after 10 ns;
    reset <= '0' after 20 ns;

    Inst_div3 : divide_by_3


      port map (
            cout   => cout,   -- Output
            clk    => clk,    -- Input
            reset  => reset   -- Iinput
        );
    end architecture

;