Makefile:如何使用命令输出作为目标名称?
我有以下生成文件:Makefile:如何使用命令输出作为目标名称?,makefile,Makefile,我有以下生成文件: :PHONY Darwin Xcode Linux Cygwin all: `uname` Cygwin: echo "Making Cygwin" Scripts/Make/MakeCygwin.sh Linux: echo "Making Linux" Scripts/Make/MakeLinux.sh Darwin: echo "Making Darwin" Scripts/Make/MakeDarwin.sh
:PHONY Darwin Xcode Linux Cygwin
all: `uname`
Cygwin:
echo "Making Cygwin"
Scripts/Make/MakeCygwin.sh
Linux:
echo "Making Linux"
Scripts/Make/MakeLinux.sh
Darwin:
echo "Making Darwin"
Scripts/Make/MakeDarwin.sh
Xcode:
echo "Making Xcode"
Scripts/Make/MakeXcode.sh
但是,它不起作用:
$ make
make: *** No rule to make target ``uname`', needed by `all'. Stop.
结果是,
uname
命令没有执行。有人知道如何让它工作吗?像这样的东西应该可以工作:
UNAME=$(shell uname)
all: ${UNAME}
您可以在这里找到更多有用的函数:gnumake的函数扩展允许您使用$(shell uname)