Module Verilog寄存器代码错误-条件检查

我正在测试一个8位寄存器的模块，与代码的其余部分分开。我正在使用ModelSim设置值，然后运行以查看结果。 这个模块应该有一个二进制数输入、一个清除位、一个启用位和一个输出

module Register8bit(D, Clk, Clear, Enable, OutNum);
    input [7:0] D; //8 bit binary data
    input Clk;       //Clock
    input Clear;     //Clear bit
    input Enable;    //Enable bit
    output reg [7:0] OutNum;

always @(posedge Clk)
begin
    if (Enable)
        begin
            if (Clear)
                OutNum <= 8'b00000000;
            else
                OutNum <= D;
        end
end
endmodule

第一步可行，但第二步不行（所以其余的也不行）。具体来说，OutNum在第二步中保持未定义状态。如果Enable为true，则使用输入数据更新OutNum在第一步中不起作用

我应该如何修复此模块

试验台代码：

`timescale 1ns / 1ps

module test_register;

//inputs
reg [7:0] D;
reg Clk;
reg Clear;
reg Enable;

//outputs
reg [7:0] OutNum;

//instantiate
Register8bit uut(
    .D(D),
    .Clk(Clk),
    .Clear(Clear),
    .Enable(Enable)
);

initial begin
    D = 10001111;
    Clk = 1;

    //step 1
    #100;
    Clear = 0;
    Enable = 0;
    #100;

    //step 2
    Clear = 0;
    Enable = 1;
    #100;

    //step 3
    Clear = 1;
    Enable = 0;
    #100;

    //step 4
    Clear = 1;
    Enable = 1;
    #100;

    //step 5
    Clear = 0;
    Enable = 1;
    #100;
end
endmodule

---

您需要多次切换

Clk

信号。您的代码只是将其设置为1，然后对整个sim卡将其保留为1

module test_register;

//inputs
reg [7:0] D;
reg Clk;
reg Clear;
reg Enable;

//outputs
reg [7:0] OutNum;

//instantiate
Register8bit uut(
    .OutNum  (OutNum),  // <---- added missing output
    .D(D),
    .Clk(Clk),
    .Clear(Clear),
    .Enable(Enable)
);

always #50 Clk = ~Clk;

always @(negedge Clk) begin
    $display($time, " clr=%b en=%b D=%b OutNum=%b", Clear, Enable, D, OutNum);
end

initial begin
    D = 'b10001111; // <---- use 'b
    Clk = 1;

    #50;

    //step 1
    #100;
    Clear = 0;
    Enable = 0;
    #100;

    //step 2
    Clear = 0;
    Enable = 1;
    #100;

    //step 3
    Clear = 1;
    Enable = 0;
    #100;

    //step 4
    Clear = 1;
    Enable = 1;
    #100;

    //step 5
    Clear = 0;
    Enable = 1;
    #100;
    #500 $finish;
end
endmodule

/*

Prints out:

                  50 clr=x en=x D=10001111 OutNum=xxxxxxxx
                 150 clr=0 en=0 D=10001111 OutNum=xxxxxxxx
                 250 clr=0 en=1 D=10001111 OutNum=xxxxxxxx
                 350 clr=1 en=0 D=10001111 OutNum=10001111
                 450 clr=1 en=1 D=10001111 OutNum=10001111
                 550 clr=0 en=1 D=10001111 OutNum=00000000
                 650 clr=0 en=1 D=10001111 OutNum=10001111
                 750 clr=0 en=1 D=10001111 OutNum=10001111
                 850 clr=0 en=1 D=10001111 OutNum=10001111
                 950 clr=0 en=1 D=10001111 OutNum=10001111
                1050 clr=0 en=1 D=10001111 OutNum=10001111

*/

模块测试\u寄存器；
//投入
reg[7:0]D；
注册时钟；
注册清晰；
注册启用；
//输出
reg[7:0]OutNum；
//实例化
寄存器8位uut(
.OutNum（OutNum）//
module test_register;

//inputs
reg [7:0] D;
reg Clk;
reg Clear;
reg Enable;

//outputs
reg [7:0] OutNum;

//instantiate
Register8bit uut(
    .OutNum  (OutNum),  // <---- added missing output
    .D(D),
    .Clk(Clk),
    .Clear(Clear),
    .Enable(Enable)
);

always #50 Clk = ~Clk;

always @(negedge Clk) begin
    $display($time, " clr=%b en=%b D=%b OutNum=%b", Clear, Enable, D, OutNum);
end

initial begin
    D = 'b10001111; // <---- use 'b
    Clk = 1;

    #50;

    //step 1
    #100;
    Clear = 0;
    Enable = 0;
    #100;

    //step 2
    Clear = 0;
    Enable = 1;
    #100;

    //step 3
    Clear = 1;
    Enable = 0;
    #100;

    //step 4
    Clear = 1;
    Enable = 1;
    #100;

    //step 5
    Clear = 0;
    Enable = 1;
    #100;
    #500 $finish;
end
endmodule

/*

Prints out:

                  50 clr=x en=x D=10001111 OutNum=xxxxxxxx
                 150 clr=0 en=0 D=10001111 OutNum=xxxxxxxx
                 250 clr=0 en=1 D=10001111 OutNum=xxxxxxxx
                 350 clr=1 en=0 D=10001111 OutNum=10001111
                 450 clr=1 en=1 D=10001111 OutNum=10001111
                 550 clr=0 en=1 D=10001111 OutNum=00000000
                 650 clr=0 en=1 D=10001111 OutNum=10001111
                 750 clr=0 en=1 D=10001111 OutNum=10001111
                 850 clr=0 en=1 D=10001111 OutNum=10001111
                 950 clr=0 en=1 D=10001111 OutNum=10001111
                1050 clr=0 en=1 D=10001111 OutNum=10001111

*/