System verilog SystemVerilog断言中是否有任何方法可以将定时延迟作为变量定义在属性中?
我的尝试:System verilog SystemVerilog断言中是否有任何方法可以将定时延迟作为变量定义在属性中?,system-verilog,system-verilog-assertions,System Verilog,System Verilog Assertions,我的尝试: parameter int delayV[5] = '{1,2,3,4,5}; module seqChecker(input clk,input inFirst,input subS,input [31:0]index); property p1; @(posedge clk) inFirst |-> ##(delayV[index]) subS; endproperty assert property(p1); endmodule
parameter int delayV[5] = '{1,2,3,4,5};
module seqChecker(input clk,input inFirst,input subS,input [31:0]index);
property p1;
@(posedge clk) inFirst |-> ##(delayV[index]) subS;
endproperty
assert property(p1);
endmodule
随之而来的错误:
[2020-10-14 09:13:52 EDT] xrun -Q -unbuffered '-timescale' '1ns/1ns' '-sysv' '-access' '+rw'
design.sv testbench.sv
TOOL: xrun 19.09-s012: Started on Oct 14, 2020 at 09:13:52 EDT
xrun: 19.09-s012: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
@(posedge clk) inFirst |-> ##(delayV[index]) subS;
|
xmvlog: *E,NOTPAR (testbench.sv,6|45): Illegal operand for constant expression [4(IEEE)].
@(posedge clk) inFirst |-> ##(delayV[index]) subS;
|
xmvlog: *E,NOTPAR (testbench.sv,6|45): Illegal operand for constant expression [4(IEEE)].
xrun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E
and fix those identified problems to proceed. Exiting with code (status 1).
TOOL: xrun 19.09-s012: Exiting on Oct 14, 2020 at 09:13:52 EDT (total: 00:00:00)
Exit code expected: 0, received: 1
Done
那么有没有一种方法可以让“##”延迟根据输入值而变化?没有。延迟必须在编译时固定。所以,可以使用参数,但不能使用变量。