Verilog 寄存器文件模拟中缺少输出

我试图模拟一个寄存器文件。我的问题是我没有得到aData或bData的输出。我怀疑我的作业有问题，但我不确定。对Verilog来说还是有点陌生

我的模块代码：

`timescale 1ns / 1ps


module registerfile(
input  [4:0]    aAddress,
input  [4:0]    bAddress,
input  [4:0]    dAddress,
input [31:0]       dData,
input              write,
input       [3:0] status,
input              clock,
input              reset,
output reg [31:0]  aData,
output reg [31:0]  bData
);


reg [31:0] registerfile [0:31];
integer i;

initial begin
for (i = 0; i <32; i = i +1 )
    begin
    registerfile[i] = 0;
    end
end

always @ (*)
begin
    if (aAddress == 5'b00000)
        begin
        aData = 32'h0000_0000; //reg[0] already holds 0
        end
    else
        begin
        aData = registerfile[aAddress]; //contents of register file at aAddress sent out to aData
        end

end

always @ (*)
begin
    if (bAddress == 5'b00000)
        begin
        bData = 32'h0000_0000; //reg[0] already holds 0
        end
    else
        begin
        bData = registerfile[bAddress]; //contents of register file at bAddress sent out to bData
        end
end

always @ (posedge clock)
begin
    if (reset == 1)
        begin
            for (i = 0; i < 32; i = i + 1)
                begin
                registerfile[i] <= 0;
                aData = 0;
                bData = 0;
                end
        end
    else if ((write == 1) && (dAddress != 0) && (dAddress != 31)) //reserve reg 0 for 0 constant and 31 for status register
        begin
            registerfile[dAddress] <= dData; //store dData
            if (aAddress == dAddress) //handles special case
                aData <= dData;
            if (bAddress == dAddress) //handles special case
                bData <= dData;
        end

    registerfile[31] <= {28'd0, status}; //status flags
end

endmodule

---

您正在两个独立的

始终
块中分配给
aData
。你不应该那样做。同样，对于
bData

另外，在测试台中，
reset
始终为0

`timescale 1ns / 1ps


module registerfile_test;

// Inputs
reg [4:0] aAddress;
reg [4:0] bAddress;
reg [4:0] dAddress;
reg [31:0] dData;
reg write;
reg [3:0] status;
reg clock;
reg reset;

// Outputs
wire [31:0] aData;
wire [31:0] bData;

// Instantiate the Unit Under Test (UUT)
registerfile uut (
    .aAddress(aAddress), 
    .bAddress(bAddress), 
    .dAddress(dAddress), 
    .dData(dData), 
    .write(write), 
    .status(status), 
    .clock(clock), 
    .reset(reset), 
    .aData(aData), 
    .bData(bData)
);


reg [31:0] registerfile [0:31];
reg [31:0] testData1, testData2;

initial begin
    // Initialize Inputs
    aAddress = 0;
    bAddress = 0;
    dAddress = 0;
    dData = 0;
    write = 0;
    clock = 0;
    reset = 0;

    // Wait 100 ns for global reset to finish
    #100;
    testData1 = 32'hFF0F_00FF;
    testData2 = 32'h00F0_FF00;
    aAddress  =      5'b00101;
    bAddress  =      5'b00010;
    dAddress  =      5'b00110;
    dData     = 32'hFFFF_FFF0; //used to test
    write     =             1;
    status    =       4'b0000;
    //write     =             0;

    registerfile[aAddress] = testData1;
    registerfile[bAddress] = testData2;
    end

    // Add stimulus here    
    always begin
    #10 clock = ~clock;
    end


endmodule