减去两个32位输入时出现Icarus Verilog语法错误？

我在学习Verilog的第一周经历了一段非常令人沮丧的经历

我试图编译下面的代码-来自mipsalu.v

module MIPSALU (ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
  always @(ALUctl, A, B) //reevaluate if these change
    case (ALUctl)
      0: ALUOut <= A & B;
      1: ALUOut <= A | B;
      2: ALUOut <= A + B;
      3: ALUOut <= A ^ B;
      6: ALUOut <= A – B;
      7: ALUOut <= A < B ? 1:0;
      12: ALUOut <= ~(A | B); // result is nor
      default: ALUOut <= 0; //default to 0, should not happen;
    endcase
endmodule

当我删除有问题的行并再次编译时，没有错误-

module MIPSALU (ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
  always @(ALUctl, A, B) //reevaluate if these change
    case (ALUctl)
      0: ALUOut <= A & B;
      1: ALUOut <= A | B;
      2: ALUOut <= A + B;
      3: ALUOut <= A ^ B;
      //6: ALUOut <= A – B;
      7: ALUOut <= A < B ? 1:0;
      12: ALUOut <= ~(A | B); // result is nor
      default: ALUOut <= 0; //default to 0, should not happen;
    endcase
endmodule

模块MIPSALU（ALUctl、A、B、ALOUT、零）；
输入[3:0]ALUctl；
输入[31:0]A，B；
输出寄存器[31:0]输出；
输出零；
分配零=（ALOUT==0）//如果ALOUT为0，则零为真；去任何地方
始终@（ALUctl，A，B）//如果这些更改，请重新评估
案例（ALUctl）
0:ALOUT不确定您是如何做到的，但您的
–
是ISO 8859-1下扩展ASCII中的一个字符。根据ASCII码，数字为150 DEC（HTML码
–；
）。Verilog预期的是
-
ASCII代码编号为45 DEC（HTML代码
-；
）

两者看起来几乎相同– （
–；
）仅比-（
-；
）长几像素，至少在某些字体中是这样

可能是您的文本编辑器在动态更改它，认为破折号看起来比减号更可读


仅供参考：在Verilog中，您通常希望将组合逻辑分配给阻塞分配（
=
），将顺序逻辑分配给非阻塞分配（
哇，这非常有用。我没有编写此代码，但我一定会将非阻塞分配改为常规=分配
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
  always @(ALUctl, A, B) //reevaluate if these change
    case (ALUctl)
      0: ALUOut <= A & B;
      1: ALUOut <= A | B;
      2: ALUOut <= A + B;
      3: ALUOut <= A ^ B;
      //6: ALUOut <= A – B;
      7: ALUOut <= A < B ? 1:0;
      12: ALUOut <= ~(A | B); // result is nor
      default: ALUOut <= 0; //default to 0, should not happen;
    endcase
endmodule