秒表verilog-警告

有人能帮我做以下警告吗

WARNING:Xst:2677 - Node <ok1> of sequential type is unconnected in block <Control>.
WARNING:Xst:2677 - Node <ok2> of sequential type is unconnected in block <Control>.
WARNING:Xst:2677 - Node <bloc/ok3> of sequential type is unconnected in block <Main>.
WARNING:Xst:2677 - Node <bloc/ok0> of sequential type is unconnected in block <Main>.
WARNING:Xst:2677 - Node <bloc/seen> of sequential type is unconnected in block <Main>.
WARNING:Xst:2677 - Node <bloc/ok> of sequential type is unconnected in block <Main>.
WARNING:Xst:2677 - Node <bloc/i_3> of sequential type is unconnected in block <Main>.
WARNING:Xst:2677 - Node <bloc/i_2> of sequential type is unconnected in block <Main>.
WARNING:Xst:2677 - Node <bloc/i_1> of sequential type is unconnected in block <Main>.
WARNING:Xst:2677 - Node <bloc/i_0> of sequential type is unconnected in block <Main>.

---

您需要使用Verilog非阻塞分配运算符

当您的节点没有到输出的路径时，通常会出现此警告。例如，当您将变量声明为16位，但仅将变量的8位分配给顶层模块的输出时。根据你分享的内容，我猜控制不是最重要的模块

检查从这些信号到顶部模块的路径，并验证它们到输出的路径是否正确

请注意，有时虽然这些路径存在于代码中，但合成器会对它们进行优化

更多信息请点击此处：

为什么他“需要”使用它？在创建时钟逻辑时这样做是一种很好的做法，但我不确定它是否/如何与这些错误相关。我同意Tim的观点。最好使用
请共享
Main
。警告可能来自合成期间的优化输出逻辑。
module Control(
    startstop,
    clk,
    reset,
    PB_1,
    PB_2,
    PB_3,
    out_control,
    out_numarator,
    seen
);
input reset;
input startstop;
input clk;
input PB_1;
input PB_2;
input PB_3;
output reg [15:0] out_control;
input wire [15:0] out_numarator;
output seen;
reg seen=0;
reg [3:0] i=0;

reg ok0=0;
reg ok=0;
reg ok1=0;
reg ok2=0;
reg ok3=0;

reg [15:0] b1_var=0;
reg [15:0] b2_var=0;
reg [15:0] b3_var=0;

always@(posedge clk)
begin
    if (startstop==1) //BLOCUL PENTRU BUTONUL DE STARTSTOP
    begin
        ok=1;
        seen=1;
    end

    if(ok==1&&startstop==0)
    begin
        i=i+1;
        ok=0;
    end

    if(seen==1||reset==1)
        out_control=out_numarator;

    if(i==1&&ok0==0)//PRIMA APASARE A BUTONULUI STARTSTOP-- PORNESTE NUMARAREA
    begin
        b1_var=0;
        b2_var=0;
        b3_var=0;
        ok0=1;
        ok1=0;
        ok2=0;
        ok3=0;
    end
    if(i==2&&ok1==0)//A DOUA APASARE ---MEMOREAZA 
    begin
        b1_var=out_numarator;
        ok1=1;
    end
    if( i==3&&ok2==0)//A 3-A APASARE --MEMOREAZA
    begin
        b2_var=out_numarator;
        ok2=1;
    end
    if(i==4&&ok3==0)// A 4-A APASARE MEMOREAZA SI OPRESTE CRONOMETRUL
    begin
        b3_var=out_numarator;
        ok3=1;
        seen=0;
        i=0;
        ok0=0;
    end

    if(reset==1)
    begin
        ok=0;
        ok0=0;
        ok1=0;
        ok2=0;
        ok3=0;
        b1_var=0;
        b2_var=0;
        b3_var=0;
        i=0;
        seen=0;
    end

    if(PB_1==1)
    begin
        out_control=b1_var;
    end

    if(PB_2==1)
    begin
        out_control=b2_var;
    end

    if(PB_3==1)
    begin
        out_control=b3_var;
    end

end

endmodule