Verilog 错误[USF XSim 62]，[Vivado 12-4473]，[VRFC 10-529]，[VRFC 10-1146]，[XSim 43-3322]
这是我的设计代码Verilog 错误[USF XSim 62]，[Vivado 12-4473]，[VRFC 10-529]，[VRFC 10-1146]，[XSim 43-3322],verilog,Verilog,这是我的设计代码 module lab2_4bit_adder( input [3:0] A, inout [3:0] B, input C0, input [3:0] B1, input Switch, inout [3:0] B2, output [3:0] S, output C4 ); wire C1; wire C2; wire C3; assig
module lab2_4bit_adder(
input [3:0] A,
inout [3:0] B,
input C0,
input [3:0] B1,
input Switch,
inout [3:0] B2,
output [3:0] S,
output C4
);
wire C1;
wire C2;
wire C3;
assign B2 = ~B1 + 1'b1;
assign B = (Switch == 0)? B1:B2;
assign B = (Switch == 1)? B2:B1;
assign B = Switch? B2:B1;
lab2_1bit_adder fa0(A[0], B[0], C0, S[0], C1);
lab2_1bit_adder fa1(A[1], B[1], C1, S[1], C2);
lab2_1bit_adder fa2(A[2], B[2], C2, S[2], C3);
lab2_1bit_adder fa3(A[3], B[3], C3, S[3], C4);
endmodule
module combine_simulation(
);
reg [3:0] A;
reg [3:0] B1;
reg C0;
reg Switch;
wire [3:0] S;
wire C4;
wire [3:0] B;
wire [3:0] B2;
lab2_4bit_adder dut(A,B1,C0,Switch,S,C4,B2,B);
initial begin
A=4'b0101; B1=4'b0011; C0=1'b0; Switch=0; #10;
A=4'b0011; B1=4'b1001; C0=1'b0; Switch=0; #10;
A=4'b0100; B1=4'b1010; C0=1'b1; Switch=0; #10;
A=4'b0101; B1=4'b0011; C0=1'b0; Switch=1; #10;
A=4'b0011; B1=4'b1001; C0=1'b0; Switch=1; #10;
A=4'b0100; B1=4'b1010; C0=1'b1; Switch=1; #10;
end
endmodule
如何更正错误？错误消息非常有用：“非网络变量无法连接到inout端口B”。无法将变量（即reg）连接到输入输出端口；到inout端口的连接必须是网络（目前最常见的网络类型是导线） 您的代码需要一些工作。4位加法器不需要双向端口（即输入输出）。当然，
AB1C0SC4BB2assign B = (Switch == 0)? B1:B2;
assign B = (Switch == 1)? B2:B1;
您正在驾驶
BmoduleendmoduleBBB2