Verilog中的低延迟FWFT Fifo

我有下面的代码，其中我尝试在verilog中实现一个低延迟的第一个字fall-through-fifo

   reg [width-1:0]       mem [depth-1:0];

   always @ (posedge clk) begin
      if (wr_en) begin
         mem[wr_pointer[address_width-1:0]] <= #1 din;
      end
   end

   assign #1 dout = mem[rd_pointer[address_width-1:0]];

   always @ (posedge clk) begin
      if (reset) begin
         wr_pointer <= #1 0;
      end else if (wr_en) begin
         wr_pointer <= #1 wr_pointer + 1'b1;
      end
   end

   always @ (posedge clk) begin
      if (reset) begin
         rd_pointer <= #1 0;
      end else if (rd_en) begin
         rd_pointer <= #1 rd_pointer + 1'b1;
      end
   end

reg[width-1:0]mem[depth-1:0]；
始终@（posedge clk）开始
如果（wr_en）开始
mem[wr_pointer[address_width-1:0]下面的一行是异步读取：

assign #1 dout = mem[rd_pointer[address_width-1:0]];

将其更改为下面的代码，使其同步

reg [width-1:0] dout;
always @ (posedge clk) begin
   if (reset) begin
      dout <= #1 0;
   end else if (rd_en) begin
      dout <= #1 mem[rd_pointer[address_width-1:0]]
   end
end

reg[width-1:0]dout；
始终@（posedge clk）开始
如果（重置）开始
阴郁的
reg [width-1:0] dout;
always @ (posedge clk) begin
   if (reset) begin
      dout <= #1 0;
   end else if (rd_en) begin
      dout <= #1 mem[rd_pointer[address_width-1:0]]
   end
end