Verilog Quartus 2-无依赖于输入/输出引脚的输出卡滞

我试图通过Quartus 2实现单周期MIPS处理器，但遇到了这些警告。时钟是我的主模块的输入，它说它不会影响任何输出。此外，我的主模块的输出卡在VCC/GND上。我想这与时钟信号有关。我认为第一个警告的原因是我没有向指令内存写入任何内容，因此您可以忽略它

那么，这些警告的常见原因是什么？有什么解决办法吗

警告（10858）：指令_内存处的Verilog HDL警告。v（7）：已使用但从未分配的对象指令。
警告（13024）：输出引脚卡在VCC或GND上
警告（21074）：设计包含1个不驱动逻辑的输入引脚
警告（15610）：无输出取决于输入引脚“clk”

我的测试台：

`timescale 1ps/1ps
module mips32_testbench();

wire [31:0] instr;
wire [31:0] R;
wire [31:0] PC;
reg [31:0] counter;
reg  clk,clk2;

mips32_single_cycle i0 (.PC_new(PC) ,.instruction(instr) ,  .result(R) , .clk(clk) );

always
begin
    #8 clk = ~clk;
end

always
begin
    #24 clk2 = ~clk2;
end

initial
begin
    clk = 0;
    clk2 = 0;
    counter = -1;
    $readmemb("registers.mem", i0.MR0.registers);
    $readmemb("instructions.tv", i0.IM1.instructions);
    $readmemb("datas.mem", i0.ALU1.LW1.DM1.datas);
end

always @(posedge clk2)
begin
    //empty
end

always @(negedge clk2)
begin
    $display("PC = %5b \n", PC[4:0]);

    $display("opcode = %6b, rs = %5b, rt = %5b, rd= %5b, immediate = %16b , address = %26b ,funct = %6b \n",instr[31:26], instr[25:21], instr[20:16], instr[15:11], instr[15:0] , instr[25:0] ,instr[5:0] );

    $display("result = %32b \n", i0.result);

    counter <= counter + 1 ;

    if(PC === 32'b00000000000000000000000000001011)begin
        $writememb("regLast.mem",i0.MR1.registers);
        $writememb("dataLast.mem",i0.ALU1.LW1.DM1.datas);
        $display("%d tests completed. \n",counter);
        $finish;
    end
end

endmodule 

编辑：我添加了接收时钟信号的模块：

module alu32_2 (data_address ,PC_new , R ,select_Rtype ,select_IJtype ,rs ,rt ,instr ,PC ,clk);
input [31:0] rs,rt;
input [31:0] instr;
input [2:0]  select_IJtype, select_Rtype;
input [31:0] PC;
input clk;

output [31:0] R , PC_new;
output [7:0] data_address;

wire [31:0] I0,I1,I2,I3,I4,I5,I6,I7;
wire ZANDI,ZORI,ZADDIU;
wire OADDIU;
wire CADDIU;
wire [31:0] EXT;
wire overflow;
wire zero;

zeroextendimm  EXT1 (EXT , instr[15:0] );


Rtype_alu_controller  ROC1 (overflow , zero ,I0 ,select_Rtype ,rs ,rt ,instr[10:5]);
and32                 AND1 (ZANDI,I1,rs,EXT);
or32                  OR1  (ZORI,I2,rs,EXT);
add32                 ADD1 (OADDIU,ZADDIU,CADDIU,I3,rs,EXT,1'b0);
loadword              LW1  (I4,instr[20:16],rs,instr[15:0],clk);
storeword             SW1  (I5,data_address,instr[20:16],rs,instr[15:0],clk);
beq                     BEQ1 (I6,PC,rs,rt,instr[15:0]);
j                     J1   (I7,PC,instr[25:0]);

mux81_32bit M1 (R,I0,I1,I2,I3,I4,I5,I6,I7,select_IJtype);
nextPC NPC (PC_new ,I6 , I7 , PC ,select_IJtype ,clk);

endmodule

有一个文件包含32位寄存器的数据和PC计数器。这个模块应该用它来做i/o操作

module mips_registers( read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, signal_reg_write, clk ,PC_read , PC_write ,PC_write_enable);

output reg[31:0] read_data_1, read_data_2 ,PC_read;
input [31:0] write_data , PC_write;
input [4:0] read_reg_1, read_reg_2, write_reg;
input signal_reg_write, PC_write_enable ,clk;

reg [31:0] registers [32:0];


wire [5:0] rr1,rr2,wr1;

zeroextend_1bit ZE1_1 (rr1 , read_reg_1);
zeroextend_1bit ZE1_2 (rr2 , read_reg_2);
zeroextend_1bit ZE1_3 (wr1 , write_reg);

always@ (posedge clk) begin
    if(1 == signal_reg_write)begin
        registers[wr1] <= write_data;
    end
    if(1 == PC_write_enable)begin
        registers[6'b100000] <= PC_write;
    end
end

always@ (negedge clk) begin
    read_data_1 <= registers[rr1];
    read_data_2 <= registers[rr2];
    PC_read <= registers[6'b100000];
end

endmodule 

---

在回答这个问题之前，假设你有一台电脑，或者任何一块带有处理器的板。清除它拥有的任何类型的内存，包括引导内存和任何可以在其中存储数据的芯片或板上的内存。现在打开电源。怎么搞的？现在应用时钟，您看到系统功能有任何变化吗？我想现在你已经找到了你问题的答案

简短回答：由于您无法在未正确初始化指令/数据内存的情况下更改结果，因此

clk

中的任何更改都不会导致输出的更改，因此Quartus软件会发出这些警告

此时，我将告诉您Quartus 2或Quartus Prime何时给出这些警告：

13024:Quartus软件在输出永远不变时发出此警告（给定当前系统和任何可能的输入）

21074：输入中的任何更改都不会影响结果或逻辑状态（顾名思义）

15610：顾名思义

现在让我从原因开始：

我尝试合成您的指令内存，它会合成，但Quartus软件假定内存中充满了0，并给出以下警告（如预期的那样）：

那么，这意味着什么？ 正如在评论中所建议的，最常见的原因可能是，可能您没有在逻辑中使用输入，显然您的情况并非如此。 但是，即使指令内存的clk和PC输入在其逻辑中使用，我们也有相同的警告，因为指令内存的每一位在默认情况下都初始化为0（尽管您从未这样做过），因此PC的任何值，无论您是哪个

negedge clk

，它输出相同的

read\u指令

，该指令始终为零且明显恒定。Quartus软件看到此情况并发出警告

现在检查你的数据存储器，你初始化了吗<斯特朗>不因此您的数据内存在开始时也充满了0（指令内存总是充满了0）。从您的设计可以看出，您的处理器除了

clk

之外没有任何输入

---

您的内存最初填充为零，然后启动系统，结果会发生什么变化（尝试用0替换您使用的所有指令，另外数据内存从0开始）

您未能使用相应的$readmem编译测试台代码，或者该文件没有初始化所有内存。另外，如果您从未使用过

clk

输入，那么它有什么意义呢？我不明白您关注的重点。我使用的是

clk

输入，但它说它不驱动任何逻辑，这是这里的问题。编译器不会给出任何错误，但会给出我上面描述的警告。文件初始化内存（我检查）但是带有

clk

输入的模块不能正常工作。我是否在时钟使用方面做错了什么？未使用的时钟使我认为可能存在逻辑问题或未完成的模块。我不知道这是不是真的，只是一个危险信号。如果有一个未完成的模块，那么不会有编译错误吗？如果你愿意，如果这些模块不足以澄清问题，我可以上传我的HORE项目@Serge您的约束中可能有一个命名错误的pin。检查约束文件是否具有名为“clk”的pin

module instruction_memory ( read_instruction, PC, clk );

output reg[31:0] read_instruction;
input [31:0] PC;
input clk;

reg [31:0] instructions [31:0];

always@ (negedge clk) begin
    read_instruction <= instructions[PC[4:0]];
end

endmodule 

module data_memory ( read_data , write_data, memoryaddress, signal_write_data, clk );

output reg[31:0] read_data;
input [31:0] write_data;
input [7:0] memoryaddress;
input clk , signal_write_data;

reg [31:0] datas [255:0];

always@ (posedge clk) begin
    if(1 == signal_write_data)begin
        datas[memoryaddress] <= write_data;
    end
end

always@ (negedge clk) begin
    read_data <= datas[memoryaddress];
end

endmodule 

module alu32_2 (data_address ,PC_new , R ,select_Rtype ,select_IJtype ,rs ,rt ,instr ,PC ,clk);
input [31:0] rs,rt;
input [31:0] instr;
input [2:0]  select_IJtype, select_Rtype;
input [31:0] PC;
input clk;

output [31:0] R , PC_new;
output [7:0] data_address;

wire [31:0] I0,I1,I2,I3,I4,I5,I6,I7;
wire ZANDI,ZORI,ZADDIU;
wire OADDIU;
wire CADDIU;
wire [31:0] EXT;
wire overflow;
wire zero;

zeroextendimm  EXT1 (EXT , instr[15:0] );


Rtype_alu_controller  ROC1 (overflow , zero ,I0 ,select_Rtype ,rs ,rt ,instr[10:5]);
and32                 AND1 (ZANDI,I1,rs,EXT);
or32                  OR1  (ZORI,I2,rs,EXT);
add32                 ADD1 (OADDIU,ZADDIU,CADDIU,I3,rs,EXT,1'b0);
loadword              LW1  (I4,instr[20:16],rs,instr[15:0],clk);
storeword             SW1  (I5,data_address,instr[20:16],rs,instr[15:0],clk);
beq                     BEQ1 (I6,PC,rs,rt,instr[15:0]);
j                     J1   (I7,PC,instr[25:0]);

mux81_32bit M1 (R,I0,I1,I2,I3,I4,I5,I6,I7,select_IJtype);
nextPC NPC (PC_new ,I6 , I7 , PC ,select_IJtype ,clk);

endmodule

Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "read_instruction[0]" is stuck at GND
Warning (13410): Pin "read_instruction[1]" is stuck at GND
Warning (13410): Pin "read_instruction[2]" is stuck at GND
Warning (13410): Pin "read_instruction[3]" is stuck at GND
Warning (13410): Pin "read_instruction[4]" is stuck at GND
Warning (13410): Pin "read_instruction[5]" is stuck at GND
Warning (13410): Pin "read_instruction[6]" is stuck at GND
Warning (13410): Pin "read_instruction[7]" is stuck at GND
Warning (13410): Pin "read_instruction[8]" is stuck at GND
Warning (13410): Pin "read_instruction[9]" is stuck at GND
Warning (13410): Pin "read_instruction[10]" is stuck at GND
Warning (13410): Pin "read_instruction[11]" is stuck at GND
Warning (13410): Pin "read_instruction[12]" is stuck at GND
Warning (13410): Pin "read_instruction[13]" is stuck at GND
Warning (13410): Pin "read_instruction[14]" is stuck at GND
Warning (13410): Pin "read_instruction[15]" is stuck at GND
Warning (13410): Pin "read_instruction[16]" is stuck at GND
Warning (13410): Pin "read_instruction[17]" is stuck at GND
Warning (13410): Pin "read_instruction[18]" is stuck at GND
Warning (13410): Pin "read_instruction[19]" is stuck at GND
Warning (13410): Pin "read_instruction[20]" is stuck at GND
Warning (13410): Pin "read_instruction[21]" is stuck at GND
Warning (13410): Pin "read_instruction[22]" is stuck at GND
Warning (13410): Pin "read_instruction[23]" is stuck at GND
Warning (13410): Pin "read_instruction[24]" is stuck at GND
Warning (13410): Pin "read_instruction[25]" is stuck at GND
Warning (13410): Pin "read_instruction[26]" is stuck at GND
Warning (13410): Pin "read_instruction[27]" is stuck at GND
Warning (13410): Pin "read_instruction[28]" is stuck at GND
Warning (13410): Pin "read_instruction[29]" is stuck at GND
Warning (13410): Pin "read_instruction[30]" is stuck at GND
Warning (13410): Pin "read_instruction[31]" is stuck at GND
Warning (21074): Design contains 33 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "PC[0]"
Warning (15610): No output dependent on input pin "PC[1]"
Warning (15610): No output dependent on input pin "PC[2]"
Warning (15610): No output dependent on input pin "PC[3]"
Warning (15610): No output dependent on input pin "PC[4]"
Warning (15610): No output dependent on input pin "PC[5]"
Warning (15610): No output dependent on input pin "PC[6]"
Warning (15610): No output dependent on input pin "PC[7]"
Warning (15610): No output dependent on input pin "PC[8]"
Warning (15610): No output dependent on input pin "PC[9]"
Warning (15610): No output dependent on input pin "PC[10]"
Warning (15610): No output dependent on input pin "PC[11]"
Warning (15610): No output dependent on input pin "PC[12]"
Warning (15610): No output dependent on input pin "PC[13]"
Warning (15610): No output dependent on input pin "PC[14]"
Warning (15610): No output dependent on input pin "PC[15]"
Warning (15610): No output dependent on input pin "PC[16]"
Warning (15610): No output dependent on input pin "PC[17]"
Warning (15610): No output dependent on input pin "PC[18]"
Warning (15610): No output dependent on input pin "PC[19]"
Warning (15610): No output dependent on input pin "PC[20]"
Warning (15610): No output dependent on input pin "PC[21]"
Warning (15610): No output dependent on input pin "PC[22]"
Warning (15610): No output dependent on input pin "PC[23]"
Warning (15610): No output dependent on input pin "PC[24]"
Warning (15610): No output dependent on input pin "PC[25]"
Warning (15610): No output dependent on input pin "PC[26]"
Warning (15610): No output dependent on input pin "PC[27]"
Warning (15610): No output dependent on input pin "PC[28]"
Warning (15610): No output dependent on input pin "PC[29]"
Warning (15610): No output dependent on input pin "PC[30]"
Warning (15610): No output dependent on input pin "PC[31]"
Warning (15610): No output dependent on input pin "clk"